Table of Contents
Advertisement
N/S*
B/W*
- (output, three-state).
Not
used.
Trappi ng of System
Mode i nst ruct ions is done
independently of this out-
put, which is designed pri-
marily to di st i ngui sh phy-
si cal
memory
spaces
for
Normal and System Modes.
- (output, three-state).
Used in t he norma
1
way to
distinguish byte or word
memory references.
BUSAK*
- (output). Not used.
How-
ever, it is connected to
di sab1e P2 buffers if the
BUSRQ* is used by an exter-
nal device.
NMI*
- (input). Used by the break-
point,
single-step
and
break swi tch funct ions to
force control back to the
Monitor program.
VI*
- (input). Not used.
NV1*
- (input). Not used.
STO-·ST3 -
(outputs, three-state).
M1*
- (input). Not used.
Only three of the ten pos-
sible conditions meaningful
for the AmZ8002 are used
on-board:
1) I/O reference
is
used
with
R/W*
and DS* as
described under DS*
2) memory refresh
becomes
RFSH* and is used on the
RAM
3) instruction fetch, first
word, becomes IF 1* and
is used in t he hardware
breakpoint
and
single-
step functions.
WAIT*
- (i nput). Used to generate
Wait states between the T2
and T3 clock cycl es of a
memory cycl e duri ng memory
references
to
address 0-
5FFF.
STOP*
- (input). Not used. It stops
the
CPU
entirely,
which
prevents the Monitor pro-
gram from executing.
BUSRQ*
- (input). Not used on-board
since only the CPU controls
the system buses.
4-2
MO*
- (output). Not used.
RESET*
- (i nput) •
Connected to the
RST*
line on the board,
which resets the CPU and
all other programmable cir-
cuits during power-up.
4-3. BUS STRUCTURE
The CPU's 16-bit multiplexed address/
data pi ns are demul t i pl exed into sep-
arate 16-bit data and address buses, as
shown in fi gure 4-2.
The address bus
is latched and the data bus is buffered
before use on the board and termination
at the P2 edge connector. A transparent
latch instead of a register is used on
the buffered address bus so that ad-
dresses may become valid before the
trailing edge of the address strobe
(AS*).
The status 1i nes and control strobes
are also buffered to P2.
All of these
lines
and
buses
float
to
the high
impedance
state
when
an
external
dev ice' s bus reque st (BUSRQ*) is ac-
knowledged (BUSAK*).
The CPU's data bus is separated from a
16-bit
internal
data bus
(1°0-1°16)
by a transceiver which can be disabled
by an active-low input on the 1NH*
Advertisement
Table of Contents
