Advanced Micro Computers Am96/4016 User Manual page 55

5-2. SERIAL I/O
2. Write a hex 40 to the port for a
software reset.
The definition of the status bits is as
follows:
SYNDET When Sync Detect is set for
internal sync detect, thi s bit
TxRDY Transmitter Ready indicates the
Am9551 is ready to accept a
data character or command.
3. Initialize the device by writing
new control i nformat i on as de-
scribed above.
data can be
I/O addresses
RxRDY Receiver Ready indicates the
Am9551 has received a character
on its serial input and is
ready to transfer it to the
CPU.
TxE Transmitter Empty signals the
processor that the transit
register is empty.
PE Parity Error indicates the
character stored in the receive
character buffer was rece i ved
with an incorrect number of
binary 1 bits.
OE Overrun flag is set when a byte
stored in the receiver
character register is overwrit-
ten with a new byte before
bei ng transferred to the
processor.
A readable status register maintains
information on the current operational
status of the device. Its format is
shown in table 5-8.
FE Fram i ng Error i nd i cates the
asynchronous mode byte stored
in the receiver character buf-
fer was received with incorrect
character bit format.
After initialization,
transferred using the
shown in table 5-7.
Synchronous transmission/reception is
obtained by first writing a Synchronous
Mode Cont ro1 Code fo 11
o\'ied
by one or
two 8-bit synch characters, followed by
the same Control Command format illus-
trated above. The format for the Syn-
chronous Mode Control Code is shown in
table 5-6.
If you wi sh to change the Monitor's
initialization of the P6 USART after
power-up, or if you intend to use the
P5 USART, the fo 11 owi ng steps are re-
commended:
The format for the Control Command that
follows it is shown in table 5-5.
1. Write three successive null bytes
to the control port (FE9 for P6 or
FEO for P5).
Two Am9551 USARTs provide full-dupl ex
seri a1 transmi ss i on
betwc~en
the lower
ei ght
1
i nes of the i ntel"na
1
data bus
and the P5 and P6 edge connectors.
Both the transmitter and receiver clock
inputs to these ci rcui ts come from the
Am8253 counter/timer.
In the standard Evaluation Board con-
figuration, the Am9551 at P6 devices
are initialized by the Monitor with
control bytes at power·-up, i ndepen-
dently of whether the ports are
j
umpered for RS232C or TTY compat i-
b
1
i ty. The dev ices are confi gured for
8-bit asynchronous characters with two
stop bits, parity disabled and 16x baud
rate factor. They are also enabled for
transmission and reception, with the
Request-To-Send line forced active and
without Hunt Mode. This is accom-
plished by first writing a hex CE Mode
Control Code to I/O addresses FE9 and
FED, followed by a hex
2l
Control Com-
mand to the same address (11001110 fol-
lowed by 00100111). The format for the
'Asynchronous Mode Control Code is shown
in table 5-4.
5-3