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Only three of these status outputs (2,
6 and 7) are needed by the Evaluation
Board's internal functions, but all are
available at the P2 edge connector.
The interrupt and trap structure is
part i cul arl y powerful, wi th very fast
res ponse to externa
1
dev i
CE~S
and i
1-
legal conditions.
Special instructions and har'dware fea-
tures
support
multiprogramming
and
multiprocessing.
In an asynchronous
cha in of CPUs, cri t i ca
1
l"esources can
be shared without sacrificing through-
put.
1-3. MEMORY
The Eval uat i on Board's dynami cRAM is
refreshed
by
the
CPU.
Additional
memory, ei ther dynami c
or'
stat i c, can
be added off-board through the P2 edge
connector.
AMC will supply a 64-kilo-
byte memory-expans i on board for thi s
purpose which has self-contained re-
freshing.
There is a provision for
substituting
off-board memory during
accesses to the on-board
mE~mory'
s ad-
dress space.
Depending on your use of CPU functions,
a very
1
arge amount of memory can be
used.
The CPU's 16 address lines can
directly access 64 kilobytes.
However,
if the
various
distinctions
between
operating mode (system and normal) and
memory-access status (instruction, data
and stack) are used to differentiate
memory resources, up to 384 ki lobytes
can be addressed as
illustrated
in
figure 1-4.
. 1-4. INPUT/OUTPUT
Memory space and I/O space are differ-
ent i ated by a memory-request
1
i ne and
other status outputs from the CPU.
The
CPU can use 16-bit I/O port addresses,
allowing up to 64K ports, although in
the Evaluation board implementation the
upper four address bits are not decoded
and often the lower one or two address
bits are used for sub-addressing within
peripheral circuits.
The Evaluation Board also implements
onl y 8-bi t I/O transfers on the four
top edge connectors (P3 through P6).
These are the lower 8 bits on the data
bus.
The
24
parallel
I/O
lines
of
the
Am8255A circuit at P3 can be configured
to transfer data in a variety of ways,
with or without handshaking.
In the
standard configuration, this edge con-
nector is used for up/down loading be-
tween the AmSYS 8/8 Development System
and the Evaluation Board.
The circuit
has a bi t set/reset funct i on that i n-
creases the efficiency of handshake
software.
The sockets provided for
driver or terminator circuits
allow
further characterization of these ports
for special applications.
Ground lines
are i nterl eaved wi th signa
1 1
i nes for
better noise immunity at this edge con-
nector.
The two Am9551 USART (un i versa
1
syn-
chronous/asynchronous
receiver/trans-
mitter) circuits attached to the P5 and
P6 edge connectors can be programmed
for
a broad
range
of
full-duplex,
doubly-buffered
communication
proto-
cols, with many automatic overhead fea-
tures.
The baud rate is contro
11
ed by
two of the three programmable channels
in the Am8253 counter/timer circuit.
As ment i oned above, no programmi ng of
I/O circuits
is
necessary when the
Evaluation Board is used in one of the
standard confi gurat ions ill ustrated in
figure 1-3.
The Monitor program will
initialize these circuits for you •
1-7
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