Takenaka System FS5000GE Instruction Manual page 46

10. Timing Chart
● Pixel clock timing (common in various operation modes)
[Phase relationship between clock output and data]
1 PC LK
PCLK
Clo ck output
10ns (max)
Dig ital data
12bit /
10bit /
8bit /
* 15.4ns in the case of FC 2200GE
20.8ns
in the case of FC 2200GE
(Note) The above timing represents the signal timing before being input to the input part of the interface unit (Camera Link
interface).
All the synchronization signals described in this chapter are internal signals as the synchronization signal
(FVAL,LVAL,CLK etc.) is not output to the outside in the case of GigE camera.
● Horizontal timing (Common in each operation mode)
Horizontal timing
ＨＤ
（I nte rn al h ori zo nt al
s ync hr on ou s s ig na l ）
Internal
signal
ＣＣＤ output signal
ＬＶＡＬ
Effective image duration
Image
output
Image signal
(Digital signal)
Unless otherwise specified, the time unit of the values in the horizontal timing chart is CLK (1/32.5MHz = 30.77nS).
※
(Note) Excluding the case that the trigger signal (Vint) is input permitting H-reset in the asynchronous shutter mode.
Color coding (Horizontal output timing)
(Odd line）
CCD output signal
（Even line）
CCD output signal
＝
15.4 ns *
316
約４． ５ 540
40 460
ＯＢ
Horizontal transfer
suspension time
約 ４ ３
Ineffective image duration （５４ ０）
（ＦＳ５０００ ＧＥ）
R G R G R G R G R
２ ４ ５ ６
Effective image
G B G B G B G B G
２ ４ ５ ６
Effective image
Ａ／Ｄ
PCLK
3156
１Hor izo ntal pe riod（ １Ｈ）
28
１２
ＯＢ
Dummy
bit
524
G R G R G R G R G
B G B G B G B G B
- 46 -
８～１２ｂｉｔ
(LV A L,FV A L)
PCLK
2616
E ffec tiv e p ixel s
Effective image duration （２６ １６）
M10510B;46/58
L AN c on ne c to r