Freescale Semiconductor PXR4030 Manuals

Manuals and User Guides for Freescale Semiconductor PXR4030. We have 1 Freescale Semiconductor PXR4030 manual available for free PDF download: Reference Manual

Freescale Semiconductor PXR4030 Reference Manual (1434 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 22 MB

Table of Contents
3
PXR40 Microcontroller Reference Manual
30
Introduction
31
PXR40 Features
41
Chapter 1

43
- Block Diagram
  43
- Critical Performance Parameters
  44
- Low-Power Modes
  44
- Packages
  44
- Developer Environment
  62
- Memory Map
  63
- Introduction
  63
- Signal Descriptions
  67
- Pin Function Selection
  67
  - Pad Configuration Register (PCR) PA Definition
    67
  - LVDS Signal Selection
    67
- External Signal Descriptions, Pin Multiplexing, and Attributes
  69
- Detailed Signal Description
  109
  - Etpu Signals
    109
  - IRQ and GPIO Signals
    110
  - Emios Signals
    111
  - Eqadc Signals
    112
  - Flexray Signals
    112
  - Flexcan Signals
    113
  - Esci Signals
    113
  - DSPI Signals
    114
  - EBI Signals
    116
  - Reset and Clock Signals
    117
  - JTAG and Nexus Signals
    118
  - PMC and Power/Voltage Signals
    119
- Reset Sources
  121
- Reset Vector
  122
- Reset Pins
  122
Chapter 4

122
- Reset
  122
- Rstout
  123
- FMPLL Lock Gating Signal
  123
- Reset Source Descriptions
  123
  - Power-On Reset (POR)
    126
  - External Reset
    126
  - Loss of Lock
    126
  - Loss of Clock
    127
  - Core Watchdog Timer/Debug Reset
    127
  - JTAG Reset
    127
  - Software System Reset
    128
  - Software External Reset
    128
- Reset Registers in the SIU
  128
- Reset Configuration
  129
  - Reset Configuration Half Word (RCHW)
    129
    
    RCHW Overview
    129
    
    RCHW Structure
    129
  - Reset Configuration Timing
    131
  - Reset Weak Pull Up/Down Configuration
    131
Chapter 5 Power Management Controller (PMC)

133
- Introduction
  133
  - Features
    133
    
    Analog PMC_SMPS Features
    134
    
    Digital PMC_SMPS Features
    134
  - Block Diagram
    135
  - PMC Operation Modes
    135
- External Signals Description
  136
  - Signals Information
    136
- Signals Details
  136
  - Vddreg
    136
  - VDD
    137
  - Vddsyn
    137
  - Vss
    137
  - Regctl
    137
  - Regsel
    137
  - Vdd33
    137
- Memory Map/Register Definition
  138
  - Configuration Register (PMC_MCR)
    138
  - Trimming Register (PMC_TRIMR)
    140
  - Status Register (PMC_SR)
    144
- Functional Description
  146
  - PMC Internal 1.2V Voltage Regulator Selection
    147
  - PMC Bandgap
    148
  - Vddreg Lvd
    148
  - Internal Voltage Regulator
    148
  - 3.3V Vddsyn Lvd
    149
  - Voltage Regulator Controller
    150
  - 1.2V VDD Lvd
    151
  - Trimming
    152
  - Interrupts
    152
  - PMC Power-On Reset
    152
  - ADC Test Mux
    154
- Initialization
  155
- Application Information
  155
  - Regulator Example
    155
  - Hardware Design Recommendations
    156
  - Introduction
    159
Chapter 6 Frequency Modulated Phase-Locked Loop (FMPLL)

160
- Block Diagram
  160
- Features
  160
- Modes of Operation
  161
- External Signal Description
  161
- Memory Map and Registers
  161
  - Module Memory Map
    161
  - Register Descriptions
    162
    
    FMPLL Synthesizer Status Register (SYNSR)
    162
    
    FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1)
    165
    
    FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2)
    167
    
    FMPLL Synthesizer FM Control Register (SYNFMCR)
    170
- Functional Description
  172
  - General
    172
  - PLL off Mode
    172
  - Normal Mode
    172
    
    PLL Lock Detection
    173
    
    Loss-Of-Clock Detection
    174
    
    PLL Normal Mode Without FM
    175
    
    PLL Normal Mode with Frequency Modulation
    177
- Resets
  180
  - Clock Mode Selection
    180
    
    External Reset
    180
    
    Power-On Reset (POR)
    180
  - PLL Loss-Of-Lock Reset
    181
  - PLL Loss-Of-Clock Reset
    181
- Interrupts
  181
  - Loss-Of-Lock Interrupt Request
    181
  - Loss-Of-Clock Interrupt Request
    181
Chapter 7 System Integration Unit (SIU)

183
Chapter 8 System Information Module

279
- SIM Overview
  279
  - SIM Constants
    279
Chapter 9 Boot Assist Module (BAM)

281
- Overview
  281
- Features
  281
- Modes of Operation
  281
  - Normal Mode
    281
  - Debug Mode
    282
  - Internal Boot Mode
    282
  - Serial Boot Mode
    282
  - Development Bus Boot Mode
    282
- Memory Map
  282
- Functional Description
  283
Chapter 10 Interrupts and Interrupt Controller (INTC)

301
- Introduction
  301
  - Block Diagram
    301
  - Overview
    302
  - Features
    304
  - Modes of Operation
    305
    
    Software Vector Mode
    305
    
    Hardware Vector Mode
    306
- External Signal Description
  307
- Memory Map and Register Definition
  307
  - Register Descriptions
    309
    
    INTC Module Configuration Register (INTC_MCR)
    309
    
    INTC Current Priority Register (INTC_CPR)
    310
    
    INTC Interrupt Acknowledge Register (INTC_IACKR)
    310
    
    INTC End-Of-Interrupt Register (INTC_EOIR)
    311
    
    INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0-7)
    312
    
    INTC Priority Select Registers (INTC_PSR0-479)
    313
- Functional Description
  313
  - Interrupt Request Sources
    313
    
    Peripheral Interrupt Requests
    331
    
    Software Configurable Interrupt Requests
    331
    
    Unique Vector for each Interrupt Request Source
    331
  - Priority Management
    331
    
    Current Priority and Preemption
    332
    
    Lifo
    333
  - Details on Handshaking with Processor
    333
    
    Software Vector Mode Handshaking
    333
    
    Hardware Vector Mode Handshaking
    334
- Initialization and Application Information
  335
  - Initialization Flow
    335
  - Interrupt Exception Handler
    336
    
    Software Vector Mode
    336
    
    Hardware Vector Mode
    337
  - ISR, RTOS, and Task Hierarchy
    337
  - Order of Execution
    338
  - Priority Ceiling Protocol
    339
    
    Elevating Priority
    339
    
    Ensuring Coherency
    339
  - Selecting Priorities According to Request Rates
    342
    
    And Deadlines
    342
  - Software Configurable Interrupt Requests
    342
    
    Scheduling a Lower Priority Portion of an ISR
    342
    
    Scheduling an ISR on Another Processor
    343
  - Lowering Priority Within an ISR
    343
  - Negating an Interrupt Request Outside of Its ISR
    343
    
    Negating an Interrupt Request as a Side Effect of an ISR
    343
    
    Negating Multiple Interrupt Requests in One ISR
    344
    
    Proper Setting of Interrupt Request Priority
    344
  - 10Examining LIFO Contents
    344
Chapter 11 General-Purpose Static RAM (SRAM)

347
- Introduction
  347
- SRAM Operating Modes
  347
- External Signal Description
  347
- Register Memory Map
  348
- Functional Description
  348
- SRAM ECC Mechanism
  348
  - Access Timing
    349
  - Reset Effects on SRAM Accesses
    350
- Initialization and Application Information
  350
  - Example Code
    351
Chapter 12 Flash Memory Array and Control

353
- Introduction
  353
  - Block Diagram
    354
    
    Flash Memory Module
    354
  - Features
    355
  - Modes of Operation
    356
    
    Flash User Mode
    356
    
    User Test Mode
    356
- Memory Map and Registers
  356
  - Module Memory Map
    356
  - Register Descriptions
    359
    
    Module Configuration Register (Flash_X_Mcr)
    360
    
    Low/MID Address Space Block Locking Register (Flash_X_Lmlr)
    364
    
    High Address Space Block Locking Register (Flash_X_Hlr)
    366
    
    Secondary Low/MID Address Space Block Locking Register (Flash_X_Slmlr)
    368
    
    Low/MID Address Space Block Select Register (Flash_X_Lmsr)
    369
    
    Address Register (Flash_X_Ar)
    370
    
    High Address Space Block Select Register (Flash_X_Hsr)
    370
    
    Flash Bus Interface Configuration Register (FLASH_BIUCR)
    371
    
    Flash Bus Interface Access Protection Register (FLASH_BIUAPR)
    374
    
    Flash Bus Interface Configuration Register 2 (FLASH_BIUCR2)
    375
    
    User Test Register 0 (Flash_X_Ut0)
    376
    
    User Test Register 1 (Flash_X_Ut1)
    379
    
    User Test Register 2 (Flash_X_Ut2)
    379
- Functional Description
  380
  - Flash User Mode
    380
  - Flash Read and Write
    380
  - Read While Write (RWW)
    380
  - Flash Programming
    381
    
    Software Locking
    384
  - Flash Erase
    384
    
    Flash Erase Suspend/Resume
    385
  - Flash Shadow Block
    387
  - Flash Reset
    388
Chapter 13 Core (E200Z7) Overview

389
- Overview
  389
- Register Model
  389
- Cache
  392
  - Cache Overview
    392
  - Cache Registers
    393
    
    L1 Cache Control and Status Register 0 (L1CSR0)
    393
    
    L1 Cache Control and Status Register 1 (L1CSR1)
    396
    
    L1Finv0
    398
    
    L1Finv1
    399
- Mmu
  399
  - Overview
    400
  - MMU Instructions
    400
  - TLB Read Entry Instruction (Tlbre)
    400
  - TLB Write Entry Instruction (Tlbwe)
    401
  - MMU Registers
    402
    
    DEAR Register
    402
    
    MMU Control and Status Register 0 (MMUCSR0)
    402
    
    MMU Assist Registers (MAS)
    403
- Exceptions
  408
  - Exception Syndrome Register
    409
- Machine State Register
  410
  - Machine Check Syndrome Register (MCSR)
    412
- Interrupt Vector Prefix Registers (IVPR)
  415
- Interrupt Vector Offset Registers (Ivorxx)
  415
- Interrupt Definitions
  416
- 13.10 Special Features
  430
  - 1Wait Apu
    430
  - 2Volatile Context Save/Restore APU
    431
  - 3Performance Monitor
    431
Chapter 14 AMBA Crossbar Switch (XBAR)

433
- Introduction
  433
  - Overview
    433
  - Block Diagram
    434
  - Features
    434
  - Modes of Operation
    435
    
    Debug Mode
    435
    
    Normal Mode
    435
- Memory Map and Register Definition
  435
  - Register Descriptions
    436
    
    Slave General-Purpose Control Registers (Xbar_Sgpcrn)
    438
    
    Functional Description
    441
  - Master Ports
    442
    
    Fixed Priority Operation
    443
    
    Introduction
    445
    
    Features
    447
    
    Modes of Operation
    448
    
    Register Descriptions
    450
    
    Functional Description
    457
Chapter 15

458
- Read Cycles
  458
  - Introduction
    461
  - Block Diagram
    462
  - Features
    463
- Memory Map and Registers
  464
- Register Descriptions
  466
Chapter 16

467
- MPU Error Address Register, MPU Port 0 to 3 (Mpu_Earn)
  467
- MPU Region Descriptor N (Mpu_Rgdn)
  468
- MPU Region Descriptor Alternate Access Control N (Mpu_Rgdaacn)
  473
- Functional Description
  474
- AHB Error Terminations
  475
  - Introduction
    479
  - Memory Map and Registers
    480
  - Register Descriptions
    481
  - Processor Core Type (ECSM_PCT)
    482
  - ECC Configuration Register (ECSM_ECR)
    483
  - ECC Status Register (ECSM_ESR)
    484
  - ECC Error Generation Register (ECSM_EEGR)
    485
  - Flash ECC Address Register (ECSM_FEAR)
    487
  - Flash ECC Master Number Register (ECSM_FEMR)
    488
  - Flash ECC Attributes Register (ECSM_FEAT)
    489
  - RAM ECC Address Register (ECSM_REAR)
    490
  - RAM ECC Syndrome Register (ECSM_RESR)
    491
  - RAM ECC Master Number Register (ECSM_REMR)
    493
  - RAM ECC Data Register (ECSM_REDR)
    494
    
    Introduction
    497
    
    External Signal Description
    498
Chapter 18

501
- SWT Interrupt Register (SWT_IR)
  501
- SWT Window Register (SWT_WN)
  502
- SWT Counter Output Register (SWT_CO)
  503
- SWT Service Key Register (SWT_SK)
  504
  - Functional Description
    505
  - Introduction
    507
Chapter 2 Memory Map

508
- Register Descriptions
  509
Chapter 19

510
- STM Count Register (STM_CNT)
  510
- STM Channel Interrupt Register (Stm_Cirn)
  511
  - Functional Description
    512
  - Introduction
    513
  - Block Diagram
    514
Chapter 3 Signal Description

515
- Register Descriptions
  516
Chapter 20

517
Chapter 22 Flexray Communication Controller (FLEXRAY)

586
Chapter 21 Block Diagram

742
Chapter 17

743
- Features
  743
- External Signal Description
  745
- Memory Map and Register Description
  746
  - Register Descriptions
    748
Chapter 23

749
Chapter 24

813
- Flexcan Module Features
  813
- Modes of Operation
  814
- External Signal Description
  815
  - Message Buffer Structure
    818
  - Rx FIFO Structure
    822
  - Register Descriptions
    824
    
    Control Register (Flexcan_X_Ctrl)
    828
    
    Free Running Timer (Flexcan_X_Timer)
    831
    
    Rx Global Mask (Flexcan_X_Rxgmask)
    832
    
    Rx 15 Mask (Flexcan_X_Rx15Mask)
    833
    
    Error and Status Register (Flexcan_X_Esr)
    835
    
    Interrupt Masks 2 Register (Flexcan_X_Imask2)
    838
    
    Interrupt Flags 2 Register (Flexcan_X_Iflag2)
    839
    
    Interrupt Flags 1 Register (Flexcan_X_Iflag1)
    840
    
    Rx Individual Mask Registers (RXIMR0–RXIMR63)
    842
  - Transmit Process
    843
  - Receive Process
    844
  - Matching Process
    846
  - Data Coherence
    847
    
    Message Buffer Deactivation
    848
    
    Message Buffer Lock Mechanism
    849
    
    Precautions When Using Global Mask and Individual Mask Registers
    850
  - CAN Protocol Related Features
    851
    
    Time Stamp
    852
    
    Arbitration and Matching Timing
    854
    
    Modes of Operation Details
    855
    
    Module Disable Mode
    856
  - Bus Interface
    857
- Initialization/Application Information
  858
  - Flexcan Addressing and RAM Size Configurations
    859
- Introduction
  861
  - Overview
    862
  - DSPI Configurations
    864
Chapter 25

865
Chapter 30

894
- Module Disable Mode
  894
- Serial Peripheral Interface (SPI) Configuration
  895
  - Master Mode
    896
  - Receive First in First out (RX FIFO) Buffering Mechanism
    897
- Deserial Serial Interface (DSI) Configuration
  898
  - DSI Slave Mode
    899
  - DSI Deserialization
    900
  - Multiple Transfer Operation (MTO)
    901
- Combined Serial Interface (CSI) Configuration
  903
  - CSI Serialization
    904
  - CSI Deserialization
    905
- DSPI Baud Rate and Clock Delay Generation
  906
  - Peripheral Chip Select Strobe Enable (PCSS)
    908
- Transfer Formats
  909
- Continuous Serial Communications Clock
  915
- Timed Serial Bus (TSB)
  916
  - PCS Switch over Timing
    918
  - TSB Command Frame Format
    919
- Interrupts/Dma Requests
  920
  - Transfer Complete Interrupt Request
    921
  - Stop Mode (External Stop Mode)
    922
  - Slave Bus Signal Gating
    923
- Baud Rate Settings
  924
- Calculation of FIFO Pointer Addresses
  925
  - Address Calculation for the First-In Entry and Last-In Entry in the TX FIFO
    926
Chapter 26 Enhanced Serial Communication Interface (Esci)

929
- Bibliography
  929
- Overview
  930
- Features
  931
  - Modes of Operation
    932
    
    Stop Mode
    933
  - Detailed Signal Descriptions
    934
    
    Register Descriptions
    935
    
    Baud Rate Register (Esci_Brr)
    936
    
    Control Register 2 (Esci_Cr2)
    938
    
    SCI Data Register (ESCI_DR)
    940
    
    Interrupt Flag and Status Register 1 (Esci_Ifsr1)
    941
    
    Interrupt Flag and Status Register 2 (Esci_Ifsr2)
    942
    
    LIN Control Register 1 (Esci_Lcr1)
    943
    
    LIN Control Register 2 (Esci_Lcr2)
    945
    
    LIN Receive Register (Esci_Lrr)
    947
    
    Functional Description
    949
    
    Break Character Formats
    951
    
    Idle Character Formats
    952
    
    Module Clock
    953
  - Baud Rate Tolerance
    954
    
    Slower Receiver Tolerance
    955
  - SCI Mode
    956
    
    Receiver
    960
    
    Reception Error Reporting
    969
    
    Multiprocessor Communication
    970
  - LIN Mode
    971
    
    LIN Frame Formats
    972
    
    LIN RX Frame Generation
    974
    
    LIN Error Reporting
    976
    
    LIN Wakeup
    978
    
    LIN Protocol Engine Reset
    979
    
    Interrupt Request Generation
    980
    
    Overview
    983
Chapter 27 Analog to Digital Conversion Sub-System

984
- Block Diagram
  985
- Features
  986
- Modes of Operation
  987
- Normal Mode
  988
- Stop Mode
  989
- External Signal Description
  990
- Detailed Signal Descriptions
  991
- Pin Mapping to Channel Mapping
  993
  - Memory Map/Register Definition
    995
  - EQADC Register Descriptions
    998
    
    EQADC External Trigger Digital Filter Register (EQADC_ETDFR)
    999
    
    EQADC CFIFO Push Registers (EQADC_CFPR)
    1000
    
    EQADC Result FIFO Pop Registers (EQADC_RFPR)
    1001
    
    EQADC Interrupt and DMA Control Registers (EQADC_IDCR)
    1004
    
    EQADC FIFO and Interrupt Status Registers (EQADC_FISR)
    1007
    
    EQADC CFIFO Transfer Counter Registers (EQADC_CFTCR)
    1011
    
    EQADC CFIFO Status Snapshot Registers (EQADC_CFSSR)
    1012
    
    EQADC CFIFO Status Register (EQADC_CFSR)
    1014
    
    EQADC Red Line Client Configuration Register (EQADC_REDLCCR)
    1015
    
    EQADC CFIFO Registers (Eqadc_Cfxrw) (X=0, ..,5; W=0, .., 3)
    1016
    
    EQADC CFIFO0 Extension Registers (Eqadc_Cf0Erw) (W=0, .., 3)
    1019
  - On-Chip ADC Registers
    1022
    
    ADC0/1 Control Registers (ADC0_CR and ADC1_CR)
    1024
    
    ADC Time Stamp Control Register (ADC_TSCR)
    1028
    
    ADC Time Base Counter Registers (ADC_TBCR)
    1029
    
    ADC0/1 Offset Calibration Constant Registers (ADC0_OCCR and ADC1_OCCR)
    1030
    
    Alternate Configuration 1-8 Control Registers (ADC_ACR1-8)
    1031
    
    ADC0/1 Alternate Gain Registers (ADC0_AGR1-2 and ADC1_AGR1-2)
    1033
    
    ADC0/1 Alternate Offset Register (ADC0_AOR1-2 and ADC1_AOR1-2)
    1034
  - Overview
    1035
  - Data Flow in EQADC
    1036
    
    Message Format in EQADC
    1038
  - Command/Result Queues
    1049
    
    CFIFO0 Streaming Mode Description
    1052
    
    CFIFO Common Prioritization and Command Transfer
    1057
    
    CFIFO Prioritization in Abort Mode
    1059
    
    Hardware Trigger Event Detection
    1060
    
    CFIFO and Trigger Status
    1065
  - EQADC Result Fifos
    1073
    
    Distributing Result Data into Rfifos
    1076
  - On-Chip ADC Configuration and Control
    1077
    
    ADC Clock and Conversion Speed
    1078
    
    Time Stamp Feature
    1080
    
    ADC Calibration Feature
    1081
    
    ADC Control Logic Overview and Command Execution
    1083
  - Internal/External Multiplexing
    1086
    
    External Multiplexing
    1089
  - EQADC Dma/Interrupt Request
    1092
  - Analog Sub-Block
    1095
  - Multiple Queues Control Setup Example
    1098
    
    EQADC Initialization
    1099
    
    Configuring EQADC for Applications
    1100
  - EQADC/DMAC Interface
    1102
    
    Rqueue/Rfifo Transfers
    1103
  - Sending Immediate Command Setup Example
    1104
  - Modifying Queues
    1105
  - Cqueue and Rqueues Usage
    1106
  - ADC Result Calibration
    1108
  - Example
    1109
  - EQADC Versus QADC
    1110
    
    Overview
    1115
    
    Features
    1118
Chapter 28 Freeze Mode

1119
- Decimation Filter Register Descriptions
  1121
- Decimation Filter Output
  1140
- Bypass Operation
  1141
- Timestamp Data Transmission
  1142
- Soft Reset Command
  1143
- Rounding
  1145
  - Integrator
    1149
  - Integrator Output
    1150
  - Integrator Reset
    1151
- Cascade Mode
  1152
  - Example Configurations
    1154
  - Cascade Freeze, Stop, and Configuration Change Procedures
    1155
- Enhanced Debug Monitor Description
  1156
  - Eqadc Configuration / Decimator Output
    1158
- Use Cases
  1159
  - Initialization Procedure
    1162
  - Saturation
    1163
    
    Use Case 2 - Input/Output From/To the CPU/DMA, Stored Data Filtering
    1165
    
    Introduction
    1169
    
    Overview
    1170
Chapter 29

1172
- Etpu Engine
  1172
- Features
  1175
- Etpu Enhancements over TPU3
  1178
- Modes of Operation
  1179
- Etpu Mode Selection
  1180
  - External Signal Description
    1181
  - Time Base Clock Signal — TCRCLK
    1182
  - Memory Map/Register Definition
    1183
- System Configuration Registers
  1187
- Time Base Registers
  1195
- Engine Related Registers
  1201
  - ETPUIDLER - Etpu Idle Register
    1202
- Global Channel Registers
  1203
- Channel Configuration and Control Registers
  1210
- Host Interface
  1216
  - Parameter Access
    1218
  - SDM Organization
    1219
  - Host Service Requests
    1221
  - Bus Error Conditions
    1223
  - Channel Priority Schemes
    1224
  - Time Slot Latency
    1230
  - Host Side Atomic Access
    1231
  - SDM Arbitration
    1232
  - Enhanced Digital Filter - EDF
    1233
- Time Bases
  1235
  - Timer Count Register 2 - TCR2
    1236
  - STAC Interface
    1239
  - GTBE - Global Time Base Enable
    1241
- Safety Features
  1242
- Performance Monitoring Features
  1243
- MISC Algorithm
  1260
- Introduction
  1263
- Signal Naming
  1264
  - Module Disable Mode
    1265
  - Multiplexed Address on Data Bus Mode
    1266
  - Debug Mode
    1267
- Address/Data Bus Configurations
  1268
  - D_ADD_DAT [0:31] — Data Lines 0-31
    1269
  - D_TS — Transfer Start
    1270
  - Memory Map/Register Definition
    1271
  - Register Descriptions
    1272
  - EBI Transfer Error Status Register (EBI_TESR)
    1273
  - EBI Bus Monitor Control Register (EBI_BMCR)
    1274
  - EBI Base Registers (EBI_CAL_BR0-3)
    1275
  - EBI Option Registers (EBI_CAL_OR0-3)
    1277
  - Functional Description
    1278
  - Bit Data Bus (16-Bit Data Bus Mode also Supported)
    1279
  - Burst Support (Wrapped Only)
    1280
  - Port Size Configuration Per Chip Select (16 or 32 Bits)
    1281
  - Slower-Speed Clock Modes
    1282
  - Optional Automatic D_CLKOUT Gating
    1283
- Reset
  1284
  - Burst Transfer
    1292
  - Small Accesses (Small Port Size and Short Burst Length)
    1297
  - Size, Alignment and Packaging on Transfers
    1301
  - Termination Signals Protocol
    1303
  - Non-Chip-Select Burst in 16-Bit Data Bus Mode
    1305
  - Calibration Bus Operation
    1306
  - Misaligned Access Support
    1307
  - Address Data Multiplexing
    1310
  - Initialization/Application Information
    1311
- Running with SDR (Single Data Rate) Burst Memories
  1312
  - Timing and Connections for Asynchronous Memories
    1313
- Connecting an MCU to Multiple Memories
  1314
- Summary of Differences from Mpc5Xx
  1315
  - Introduction
    1317
  - Block Diagram
    1318
  - Features
    1319
  - Modes of Operation
    1320
Chapter 31

1321
- Nexus Reset Mode
  1321
- Detailed Signal Descriptions
  1322
- Ready (RDY)
  1323
- NDI Functional Description
  1327
  - Configuring the NDI for Nexus Messaging
    1328
  - Programmable MCKO Frequency
    1329
- Nexus Port Controller (NPC)
  1330
- NPC Memory Map and Register Definition
  1331
  - Register Descriptions
    1332
  - Nexus Device ID Register (DID)
    1333
- NPC Functional Description
  1335
  - Output Messages
    1336
  - Ieee 1149.1-2001 (Jtag) Tap
    1337
  - Nexus Auxiliary Port Sharing
    1342
  - Nexus Reset Control
    1343
- E200Z7 Class 3 Nexus Module (NZ7C3)
  1344
  - Block Diagram
    1345
  - Features
    1347
  - Tcodes Supported by NZ7C3
    1348
- NZ7C3 Memory Map and Register Definition
  1352
  - NZ7C3 Register Access Via JTAG / Once
    1353
- Ownership Trace
  1354
  - OTM Error Messages
    1355
  - Program Trace
    1356
    
    BTM Using Branch History Messages
    1357
  - BTM Message Formats
    1358
    
    Resource Full Messages
    1359
    
    Program Correlation Messages
    1360
  - Enabling Program Trace
    1362
  - Relative Addressing
    1363
  - Sequential Instruction Count (I-CNT)
    1364
    
    Data Trace
    1365
    
    DTM Message Formats
    1366
    
    DTM Operation
    1368
    
    Data Trace Timing Diagrams (Eight MDO Configuration)
    1370
    
    Watchpoint Messaging
    1371
    
    Watchpoint Error Message
    1372
    
    Single Write Access
    1373
    
    Block Write Access (Burst Mode)
    1374
    
    Block Read Access (Non-Burst Mode)
    1375
    
    Error Handling
    1376
  - Examples
    1377
  - IEEE 1149.1 (JTAG) RD/WR Sequences
    1378
    
    JTAG Sequence for Read Access of Memory-Mapped Resources
    1379
    
    Block Diagrams
    1380
  - Rules for Output Messages
    1381
  - NXDM and NXFR Registers
    1382
    
    Watchpoint Trigger Register (WT)
    1385
    
    Data Trace Start Address Registers 1 and 2 (DTSA1 and DTSA2)
    1386
    
    Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)
    1387
    
    Breakpoint / Watchpoint Control Register 2 (BWC2)
    1388
    
    Breakpoint/Watchpoint Address Registers 1 and 2 (BWA1 and BWA2)
    1389
    
    Functional Description
    1391
  - Tcodes Supported by NXDM and NXFR
    1392
    
    Data Trace
    1395
    
    DTM Operation
    1396
  - Watchpoint Support
    1397
    
    Watchpoint Messaging
    1398
    
    Introduction
    1401
    
    Overview
    1402
Chapter 32 Bypass Mode

1403
- External Signal Description
  1404
- Bypass Register
  1405
  - Boundary Scan Register
    1406
  - Enabling the TAP Controller
    1409
  - BYPASS Instruction
    1410
  - ENABLE_CENSOR_CTRL Instruction
    1411
- Boundary Scan
  1412
- Introduction
  1413
- Configuring Hardware Features
  1414
Chapter 33

1416
- Frequency Modulated PLL
  1416
  - Crossbar Switch
    1417
  - Cache
    1418
- Memory Management Unit (MMU)
  1421
- Application Software
  1422
  - Signal Processing Extension
    1424
  - Hardware Single Precision Floating Point
    1425
- Peripherals and General Application Guidelines
  1426
- Overview
  1428
Chapter 34 Temperature Formula

1430
- Registers
  1431
  - Temperature Calculation Constants Register 1
    1432

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Motherboard Computer Hardware Microcontrollers Control Unit Controller

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Table of Contents

Chapter 1

Chapter 4

Chapter 5 Power Management Controller (PMC)

Chapter 6 Frequency Modulated Phase-Locked Loop (FMPLL)

Chapter 7 System Integration Unit (SIU)

Chapter 8 System Information Module

Chapter 9 Boot Assist Module (BAM)

Chapter 10 Interrupts and Interrupt Controller (INTC)

Chapter 11 General-Purpose Static RAM (SRAM)

Chapter 12 Flash Memory Array and Control

Chapter 13 Core (E200Z7) Overview

Chapter 14 AMBA Crossbar Switch (XBAR)

Chapter 15

Chapter 16

Chapter 18

Chapter 2 Memory Map

Chapter 19

Chapter 3 Signal Description

Chapter 20

Chapter 22 Flexray Communication Controller (FLEXRAY)

Chapter 21 Block Diagram

Chapter 17

Chapter 23

Chapter 24

Chapter 25

Chapter 30

Chapter 26 Enhanced Serial Communication Interface (Esci)

Chapter 27 Analog to Digital Conversion Sub-System

Chapter 28 Freeze Mode

Chapter 29

Chapter 31

Chapter 32 Bypass Mode

Chapter 33

Chapter 34 Temperature Formula

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