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NA# Enable
This item allows you to select between two methods of chipset
NA# asserted during CPU write cycle/CPU line fills, Enabled and
Disabled.
RAS Precharge Time
DRAM must continually be refreshed or it will lose its data.
Normally, DRAM is refreshed entirely as the result of a single
request. This option allows you to determine the number of CPU
clocks allocated for the Row Address Strobe to accumulate its
charge before the DRAM is refreshed. If insufficient time is
allowed, refresh may be incomplete and data lost.
RAS to CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of
the transition from Row Address Strobe (RAS) to Column Address
Strobe (CAS).
CPU to PCI Post Write
Set this option to Enabled to give priority to posted messages from
the CPU to PCI bus.
CPU to PCI Burst Men_WR
Set this option to Enabled to allow write instructions to be com-
bined in PCI burst mode. The settings are Enabled or Disabled.
ISA Bus Clock Frequency
This item allows you to select the ISA bus clock PCICLK/3 OR
PCICLK/4.
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
enabled.
Chapter 3 Award BIOS Setup
59
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