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R O M P C I / I S A B I O S ( 2 A 5 I I A K 9 )
Auto Configuration
L2 (WB) Tag Bit Length
SRAM Back-to-BACK
NA# Enable
Starting Point of Paging
Refresh Cycle Time (us)
RAS Pulse Width Refresh : 6T
RAS Precharge Time
RAS to CAS Delay
CAS# Pulse Width (FP)
CAS# Pulse Width (EDO)
RAMW# Assertion Timing
CAS Precharge Time (FP)
CAS Precharge Time (EDO) : 1T/2T
Enhanced Memory Write
Read Prefetch Memory RD : Disabled
CPU to PCI Post Write
CPU to PCI Burst Mem.WR: Disabled
ISA Bus Clock Frequency : PCICLK/4
Auto Configuration
Set this item to Enabled to pre-defined values for DRAM, cache
timing according to CPU type & system clock. Thus, each item
value may display differently depending on your system configura-
tions.
When this item is enabled, the pre-defined items will become
SHOW-ONLY.
58
PCM-5894/5892 User Manual
C H I P S E T F E A T U R E S S E T U P
A W A R D S O F T W A R E , I N C .
: Enabled
: 8bits
: Disabled
: Disabled
: 1T
: 187.2
: 4T
:
4T
: 2T
: 1T
: 3T
: 1T/2T
: Disabled
: 3T
CHIPSET features setup
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole at 15M-16M
Boot ROM Function
Esc:Quit
F1 : Help
F5 : Old Values
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
: Enabled
: Enabled
: Disabled
: Disabled
: Select Item
PU/PD/+/- : Modify
(Shift)F2 : Color
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