Ctr1 Gate Signal; Ctr1 Out Signal; Ctr2 Clk Signal - Measurement Computing PCI-DAS6034 User Manual

PCI-DAS6034, PCI-DAS6035, and PCI-DAS6036 User's Guide

CTR1 GATE signal

You can use the CTR1 GATE signal for starting and stopping the counter, saving counter contents, etc. It is
polarity programmable and is available at the CTR1 GATE pin.
Figure 24 shows the minimum timing requirements for the CTR1 GATE signal.
Rising Edge Polarity
Falling Edge Polarity

CTR1 OUT signal

This signal is present on the CTR1 OUT pin. The CTR1 OUT signal is the output of one of the two user's
counters in an industry-standard 82C54 chip.
For detailed information on counter operations, please refer to the data sheet on our WEB page at
www.measurementcomputing.com/PDFmanuals/82C54.pdf.
Figure 25 shows the timing requirements for the CTR1 OUT signal for counter mode 0 and mode 2.
CTR1 CLK
CTR1 OUT (Mode 2)
CTR1 OUT (Mode 0)

CTR2 CLK signal

The CTR2 CLK signal can serve as the clock source for independent user counter 2. It can be selected through
software at the CTR2 CLK pin rather than using the on-board 10 MHz or 100 kHz sources. It is also polarity
programmable. The maximum input frequency is 10 MHz. There is no minimum frequency specified.
Figure 26 shows the timing requirements for the CTR2 CLK signal.
Figure 24. CTR1 GATE signal timing
Figure 25. CTR1 OUT signal timing
t =100 ns minimum
p
t t
w-H w-L
t =15 ns minimum
w-H
t =25 ns minimum
w-L
Figure 26. CTR2 CLK signal timing
t
w
t = 25 ns minimum
w
TC
27
Functional Details