Measurement Computing PCI-DAS6034 User Manual page 19

PCI-DAS6034, PCI-DAS6035, and PCI-DAS6036 User's Guide Functional Details
Except for the SYNC CLK signal, the DAQ-Sync timing and control signals are a subset of the AUXIO signals
available at the 100-pin I/O connector. These versions of the signals are used for board-to-board
synchronization and have the same timing specifications as their I/O connector counterparts. Refer to the "DAQ
signal timing" section on page 20 for explanations of signals and timing.
Use the SYNC CLCK signal to determine the master/slave configuration of a DAQ-Sync-enabled system. Each
system can have one master and up to three slaves. SYNC CLK is the 40 MHz time base used to derive all
board timing and control. The master provides this clock to the slave boards so that all boards in the DAQ-sync-
enabled system are timed from the same clock.
Figure 4. Block diagram – PCI-DAS6034, PCI-DAS6035, and PCI-DAS6036
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