RME Audio ADI-2 Pro User Manual page 71

Common interface jitter values in real
world applications are below 10 ns, a
very good value is less than 2 ns.
The screenshot shows an extremely
jittery SPDIF signal of about 50 ns jitter
(top graph, yellow). SteadyClock turns
this signal into a clock with less than 2
ns jitter (lower graph, blue). The signal
processed by SteadyClock is of course
not only used internally, but also used
to clock the digital output. Therefore
the refreshed and jitter-cleaned signal
can be used as reference clock without
hesitation.
The above numbers refer to interface jitter which is measured directly at a word clock output, or
on the digital signal itself. The so called sampling jitter, usually in the range of a few picosec-
onds, is also extremely low on the ADI-2 Pro. One way to show this is to feed a 10 kHz sine into
the analog input, then analyze the sampled result in the digital domain. If the ADC suffers from
jitter, symmetrical sidebands will be visible in the measurement. The picture below shows such
a measurement – and no sidebands at all that could possibly be audible as jitter.
User's Guide ADI-2 Pro © RME
71