Steadyclock - RME Audio ADI-2 Pro User Manual

2 channels analog / digital converter, 4 channels digital / analog converter
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It needs to be mentioned that the ADC used in the ADI-2 Pro has improved noise shaping fil-
ters, adapted to the higher sample rate range that it offers. Indeed the rise in noise over fre-
quency is much lower than in former converter chips, where for example at 192 kHz sample
rate the wideband noise measurement would not reach -92 dBFS, but only -79 dBFS.
As is common in professional Digital Audio Workstations, the level meters of the ADI-2 Pro are
band limited to 40 kHz, so do not show the excessive noise levels of 768 kHz and DSD, but
everything within the audio range and a bit above.

34.6 SteadyClock

RME's SteadyClock technology guarantees an excellent performance in all clock modes. Its
highly efficient jitter suppression refreshes and cleans up any clock signal.
Usually a clock section consists of an analog PLL for external synchronization and several
quartz oscillators for internal synchronization. SteadyClock requires one quartz only, using a
frequency not equalling digital audio. Modern circuit designs like hi-speed digital synthesizer,
digital PLL, 1 GHz sample rate and analog filtering allow RME to realize a completely newly
developed clock technology, right within the FPGA at lowest costs. The clock's performance
exceeds even professional expectations. Despite its remarkable features, SteadyClock reacts
quite fast compared to other techniques. It locks in fractions of a second to the input signal,
follows even extreme varipitch changes with phase accuracy, and locks directly within a range
of 28 kHz up to 200 kHz.
The further improved SteadyClock III technology of the ADI-2 Pro guarantees an excellent per-
formance in all clock modes. Thanks to a highly efficient jitter suppression, the AD- and DA-
conversion always operates on highest sonic level, being completely independent from the
quality of the incoming clock signal.
SteadyClock has been originally developed to gain a stable and clean clock from the heavily
jittery MADI data signal (the embedded MADI clock suffers from about 80 ns jitter). Using the
input sources of the ADI-2 Pro, ADAT, SPDIF and AES/EBU, you'll most probably never experi-
ence such high jitter values. But SteadyClock is not only ready for them, it would handle them
just on the fly.
User's Guide ADI-2 Pro © RME
70

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