D/O Port Architecture - ICP DAS USA PEX-D24 User Manual

2.5.3

D/O Port Architecture

Connector
PIO-D56/D56U
PEX-D56
The digital output control architecture for the PIO-D56/D56U and PEX-D56 is
demonstrated in Figure 2.4.

When the RESET\ signal is in the Low-state, if means that all D/O
operations are disabled.

When RESET\ signal is in the High-state, if means all D/O operations are
enabled.
The power-on states are as follows:

All DO operations are disabled

All output latches are cleared to Low-Level
PIO/PEX-D24/D56 Series User Manual (Ver.3.1, Mar. 2015, PMH-005-31)
CON1
Figure2.4 D/O Port Architecture
Description
Digital Output
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