Clocking Scheme - Nokia RM-313 Service Manual

RM-313
System Module
System power-up
After inserting the main battery, regulators started by HW are enabled. SW checks, if there is some reason to
keep the power on. If not, the system is set to power off state by watchdog. Power up can be caused by
following reasons:
• Power key is pressed
• Charger is connected
• RTC alarm occurs
• MBUS wakeup
CellMo engine (WG4.1M) is master during power up sequence i.e. CellMo side makes the decision when phone
is powered on. RSTX signal from AVilma is used to enable the startup sequence of Rel3.1 engine. The rising
edge of RSTX starts all the resources needed to boot RAPIDOYawe and OMAP2420 chips following the required
sequence:
1 When a valid wake up event happens (power key press, charger detection, RTC alarm or voltage detected
in MBUS line), AVILMA asserts RSTX signal high. RSTX enables the internal regulators of AVilma (VIO, VANA,
VDRAM and VR1), Betty, Menelaus1 and the discrete SMPS for RAPIDOYawe core. VIO enables the AVilma's
internal 32kHz output buffer and VR1 starts the 38.4MHz VCTCXO on RF. Both 32kHz sleep clock and
38.4MHz RF clock start to run and are available in the system.
2 It takes max 0.65ms before Menelaus1 is ready to start the power-up sequence on the APE side. VIO_APE
starts first. It supplies power for APE side memories and OMAP2420POP I/Os.
3 SysClkReq signal has an internal pull-up resistor to IO voltage (VIO_APE) of OMAP, so it follows the slope
of VIO_APE. RAPIDOYawe activates the 19.2MHz system clock when it interprets SysClkReq as a logical 1.
This happens when SysClkReq reaches about 1V level.
4 When VIO_APE has completed its power-up, it is possible to apply signals to OMAP I/Os. 32 kHz sleep clock
is applied to OMAP.
5 When VIO_APE has completed its power-on sequence, the VCORE_APE is enabled and starts its ramp up
sequence.
6 When VCORE_APE ramp up is complete, VPLL_APE starts ramping up.
7 When VPLL_APE has ramped up, the PWROK signal is asserted to signal that the OMAP2420 power-up
sequence has been completed.
8 After a 16ms (typ) delay, the PURX signal is asserted high by AVILMA. Both CellMo and APE processors are
released out of reset with this signal. SW can start the controlling of SW controllable regulators on the
CellMo side.
9 OMAP2420POP completes its power-on sequence, and asserts nRESWARM high (after ~5x32kHz clock
cycles) when it is completed.
10 SW can start the controlling of VMMC_APE, VAUX_APE, VADAC_APE, VDCDC3_APE, V18_APE and V28_APE
regulators of M1 via the I2C interface.

Clocking scheme

There are two main clocks in the system:
• 38.4MHz RF clock produced by VCTCXO in RF section
• 32.768kHz sleep clock produced by the EM ASIC N2200 with an external crystal.
RF clock is generated only when VCTCXO is powered on by the EM ASIC regulator. The regulator itself is
activated by SleepX signal from RAPIDO. When both CPU's are on sleep, RF clock is stopped.
RF clock is used by RAPIDOYawe, which provides 19.2MHz SysClk to the application processor. Both RAPIDO
and OMAP2420 have internal PLL's that create clock signals for other peripheral devices/interfaces like SD
card, SIM, CCP, I2C and memories.
Issue 1 COMPANY CONFIDENTIAL
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