Power Distribution; Clocking Scheme - Nokia 6233 Service Manual

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Power distribution

The power distribution is shown in the diagram below. Current consumption is measured via the Current
Gauge Resistor and the battery voltage is stabilized by means of a capacitor. The tables below specifies the
voltages.
Figure 57 Power regulator diagram

Clocking scheme

In BB5.0, two main clocks are provided to the system: 38.4MHz RF clock produced by VCTCXO in RF section
and 32.768kHz sleep clock produced by RETU with an external crystal.
32k Sleep Clock is always powered on after startup. Sleep clock is used by RAP3G and OMAP for low-power
operation.
SMPS Clk is 2.4MHz clock line from RAP3G to TAHVO. In deep sleep mode, when VCTCXO is off, this signal is
set to '0'-state.
BT Clk is 38.4MHz signal from HINKU ASIC to BT module.
CLK600 is 600KHz signal from TAHVO to APE VCORE SMPS. The clock source is internal RC oscillator in TAHVO
(during the power-up sequence) or RAP3G SMPS Clk.
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