Information On Functions Of Ic Terminals - Pioneer MEP-7000 Service Manual

5

10.30 INFORMATION ON FUNCTIONS OF IC TERMINALS

List of Items
ADSP-BF531SBSTZ400, XC3S50-4TQG144C, PDY084A8, PEG481A, PEG480A
[1] SOUTH CPU(ADSP-BF531SBSTZ400) (SMAIN ASSY : IC202)
PIN PORT NAME
1 GND1
DGND
2 GND2
DGND
3 GND3
DGND
4 VROUT1 -
5 VROUT0 -
6 VDDEXT1 V+3R3D
7 GND4
DGND
8 GND5
DGND
9 GND6
DGND
10 CLKIN CLKIN
11 XTAL XTAL
12 VDDEXT2 V+3R3D
13 /RESET RST#
14 NMI -
15 GND7
DGND
16 RTXO -
17 RTXI -
18 VDDRTC -
19 GND8
DGND
20 VDDEXT3 V+3R3D
21 PPI_CLK -
22 PPI0 -
23 PPI1 -
24 PPI2 -
25 VDDINT1 V+1R2BD
26 PPI3 -
27 PF15 DSPDREQB#
28 PF14 DSPDREQA#
29 PF13 USBIRQ#
30 GND9
DGND
31 VDDEXT4 V+3R3D
32 PF12 ATA2_IRQ
33 PF11 ATA1_IRQ
34 PF10 BRDG_CS#
35 PF9 -
36 PF8 FINIT#/SD2_OUT
37 PF7 FDONE
38 PF6 FPRGM
39 GND10
DGND
40 GND11
DGND
41 GND12
DGND
42 GND13
DGND
43 GND14
DGND
44 GND15
DGND
45 VDDEXT5 V+3R3D
46 PF5 FPGARST#
47 PF4 DSPRST#
48 PF3 STATUS LED
49 PF2 LATCHOE#
50 PF1 DSPCS#
5
6
SIGNAL NAME I/O
- GND
- GND
- GND
O Not used (open)
O Not used (open)
- I/O power supply input (3.3 V)
- GND
- GND
- GND
I CPU clock input (24.576 MHz)
O CPU clock output (24.576 MHz)
- I/O power supply input (3.3 V)
I Reset input
I Not used (connect to GND)
- GND
O Not used (open)
I Not used (connect to GND)
- Not used (connect to 3.3 V)
- GND
- I/O power supply input (3.3 V)
I Not used (connect to GND)
O Not used (open)
O Not used (open)
O Not used (open)
- CPU core power supply input (1.2 V)
O Not used (open)
I DSP data request of audio output B
I DSP data request of audio output A
I USBIC interrupt request
- GND
- I/O power supply input (3.3 V)
I FPGA-ATAPI data read request of drive 2
I FPGA-ATAPI data read request of drive 1
I Control input of control unit communication
O Not used
FPGA configuration initialization
I (top and bottom communication data are input after the initialization is
completed, but do not monitor it.)
I FPGA initialization is completed
O FPGA configuration program
- GND
- GND
- GND
- GND
- GND
- GND
- I/O power supply input (3.3 V)
O FPGA reset
O DSP reset
O LED for diagnosis
O IC351 (latch output) output enable
O DSP serial chip select
6
7
PIN FUNCTIONS
MEP-7000
7
8
A
B
C
D
E
F
237
8