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Artesyn MVME4100 Programmer's Reference Manual

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MVME4100 Single Board Computer
Programmer's Reference
P/N: 6806800H19C
June 2014

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Summary of Contents for Artesyn MVME4100

  • Page 1 MVME4100 Single Board Computer Programmer’s Reference P/N: 6806800H19C June 2014...
  • Page 2 Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes.

  • Page 3: Table Of Contents

    3.1.16 NAND Flash Chip 2 Status Register ..........42 MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 4 4.12.5 USB Oscillator Configuration ..........68 MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 5 A.10 VPD Contents for MVME4100 Boards ........
  • Page 6 Contents Contents Contents MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 7 Tick Timer Counter Register ........... . . 51 MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 8 Variable VPD Contents ............83 Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications ....85 Table B-2 Manufacturer’s Publications .
  • Page 9 Boot Flash Bank ............32 MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 10: List Of Figures

    List of Figures MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 11: About This Manual

    IDSEL mapping, interrupt assignments for the MPC8548E interrupt controller, Flash memory, two-wire serial interface addressing, and other device and system considerations. Appendix B, Related Documentation, provides a listing of related Artesyn manuals, vendor documentation, and industry specifications. Abbreviations This document uses the following abbreviations:...
  • Page 12 Repeated item for example node 1, node 2, ..., node Omission of information from example/command that is not necessary at the time being Ranges, for example: 0..4 means one of the integers 0,1,2,3, and 4 (used in registers) MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 13 Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered. Pay attention to important information MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 14: Summary Of Changes

    "Variable VPD Contents", added information on MRAM, real time clock and Quad UART, removed "Serial Presence Detect Checksum Calculation" and "SPD Contents for MVME4100 Boards", editorial changes 6806800H19C June 2014 Re- branded to Artesyn template. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 15: Introduction

    Computer. Refer to the MPC8548E Reference Manual listed in Appendix B, Related Documentation, for more detail and programming information. At the time of publication of this manual, the MVME4100 is available in the configurations shown below. Table 1-1 Board Variants...
  • Page 16 One quad UART (QUART) controller to provide four 16550- compatible, 9.6 to 115.2 Kbaud, asynchronous serial channels: four channels for rear P2 I/O Timers Four 32-bit MPC8548E timers Four 32-bit timers in a PLD MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 17 Planar status indicators One standard 16-pin COP header One standard 20-pin JTAG header Boundary scan support Switches for VME geographical addressing in a three-row backplane Software Support VxWorks OS support Linux OS support MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 18: Block Diagram

    Introduction Block Diagram The following figure is a block diagram of the MVME4100 architecture. Figure 1-1 Block Diagram MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 19: Functional Description

    The MVME4100 VMEbus board is based on the MPC8548E system-on-chip (SoC) processor. The MVME4100 provides front panel access to one serial port with a micro DB-9 connector, two 10/100/1000 Ethernet ports with two RJ-45 connectors, and one USB port with one type A connector.
  • Page 20 Introduction MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 21: Memory Maps

    Chapter 2 Memory Maps Overview The following sections describe the memory maps for the MVME4100. Refer to the MPC8548E Reference Manual for additional details and/or programming information. 2.1.1 Default Processor Memory Map The following table describes a default memory map from the point of view of the processor after a processor reset.

  • Page 22: Pci Memory Map

    The following table is the suggested PCI memory map for each PCI bus. This table reflects the address map implemented by the board level firmware at release time. Table 2-3 PCI Memory Map Processor Address Start Size Definition Notes 0000 0000 top_dram - 1 dram_size System Memory (on-board DRAM) MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 23: Vme Memory Map

    Memory Maps 2.1.4 VME Memory Map The MVME4100 is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2 GB. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 24 Memory Maps MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 25: Register Descriptions

    System resources including system control and status registers, external timers, and the QUART are mapped into a 16 MB address range accessible from the MVME4100 local bus via the MPC8548E LBC. The memory map is defined in the following table including the LBC bank chip select used to decode the register.
  • Page 26 F200 0030 PLD Revision F200 0031 Reserved F200 0032 Reserved F200 0033 Reserved F200 0034 PLD Date Code (32 bits) F200 0038 Test Register 1 (32 bits) F200 003C Test Register 2 (32 bits) MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 27 External PLD Tick Timer 3 Compare Register F202 0038 External PLD Tick Timer 3 Counter Register F202 003C Reserved F202 0040 External PLD Tick Timer 4 Control Register F202 0044 External PLD Tick Timer 4 Compare Register MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 28: System Status Register

    2. 32-bit write only. 3. Byte read/write capable. 3.1.1 System Status Register The MVME4100 has a System Status Register that is a read only register used to provide general board status information. Table 3-2 System Status Register System Status Register - 0xF200 0000...

  • Page 29: System Control Register

    A set condition indicates the switch is on. 3.1.2 System Control Register The MVME4100 has a System Control Register that provides general board control bits. Table 3-3 System Control Register System Control Register - 0xF200 0001 Field...

  • Page 30: Status Indicator Register

    3.1.3 Status Indicator Register The MVME4100 provides a Status Indicator Register that may be read by the system software to determine the state of the on-board status indicator LEDs or written to by system software to illuminate the corresponding on-board LEDs.

  • Page 31: Nor Flash Control/Status Register

    Reserved for future implementation 3.1.4 NOR Flash Control/Status Register The MVME4100 Flash Control/Status Register provides software controlled bank write protect and map select functions as well as boot block select, bank write protect, and activity status for the NOR flash.
  • Page 32 Memory Map Select. When this bit is cleared, the flash memory map is controlled by the Flash Boot Block Select switch (see the MVME4100 Installation and Use manual for switch settings). When the Map Select bit is set, boot block A is selected and mapped...

  • Page 33: Interrupt Register 1

    Register Descriptions 3.1.5 Interrupt Register 1 The MVME4100 provides an Interrupt Register that may be read by the system software to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt Table 3-6 Interrupt Register 1 Interrupt Register 1 - 0xF200 0004...

  • Page 34: Interrupt Register 2

    3.1.6 Interrupt Register 2 The RTC, TEMP sensor and Abort switch interrupts are OR'd together. The MVME4100 provides an Interrupt Register that may be read by the system software to determine which device originated the interrupt. This register also includes bits that allow the interrupt sources to be mask.

  • Page 35: Presence Detect Register

    Register Descriptions 3.1.7 Presence Detect Register The MVME4100 provides a Presence Detect Register that may be read by the system software to determine the presence of optional devices. Table 3-8 Presence Detect Register Presence Detect Register - 0xF200 0006 Field...

  • Page 36: Pci Bus Status Registers

    Register Descriptions 3.1.8 PCI Bus Status Registers The MVME4100 Status Registers provide PCI bus configuration information for each of the PCI busses. Table 3-9 PCI Bus 1 Status Register PCI Bus 1 Status Register - 0xF200 0008 Field RSVD RSVD...

  • Page 37: Table 3-11 Pci Bus 3 Status Register

    PCI-X Bus 3. A set condition indicates that bus 3 is operating in PCI-X mode. Cleared indicates PCI mode. PCI_3_64B PCI Bus 3 64-bit. A set condition indicates that bus 3 is enabled to operate in 64-bit mode. Cleared indicates 32-bit mode. RSVD Reserved for future implementation. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 38: Nand Flash Chip 1 Control Register

    Register Descriptions 3.1.9 NAND Flash Chip 1 Control Register The MVME4100 provides a Control Register for the NAND Flash device. Table 3-12 NAND Flash Chip 1 Control Register NAND Flash Chip 1 Control Register - 0xF200 0010 Field RSVD RSVD...

  • Page 39: Nand Flash Chip 1 Presence Register

    RSVD Reserved for future implementation. 3.1.11 NAND Flash Chip 1 Presence Register The MVME4100 provides a Presence Register for the NAND Flash device. Table 3-14 NAND Flash Chip 1 Presence Register NAND Flash Chip 1 Presence Register - 0xF200 0014...

  • Page 40: Nand Flash Chip 1 Status Register

    Register Descriptions 3.1.12 NAND Flash Chip 1 Status Register The MVME4100 provides a Status Register for the NAND Flash device. Table 3-15 NAND Flash Chip 1 Status Register NAND Flash Chip 1 Status Register - 0xF200 0015 Field RSVD RSVD...

  • Page 41: Nand Flash Chip 2 Select Register

    RSVD Reserved for future implementation. 3.1.14 NAND Flash Chip 2 Select Register The MVME4100 provides a Select Register for the NAND Flash device. Table 3-17 NAND Flash Chip 2 Select Register NAND Flash Chip 2 Select Register - 0xF200 0019...

  • Page 42: Nand Flash Chip 2 Presence Register

    Register Descriptions 3.1.15 NAND Flash Chip 2 Presence Register The MVME4100 provides a Presence Register for the NAND Flash device. Table 3-18 NAND Flash Chip 2 Presence Register NAND Flash Chip 2 Presence Register - 0xF200 001C Field RSVD RSVD...

  • Page 43: Watch Dog Timer Load Register

    Ready/Busy 1. If cleared, Device 1 is busy. If set, device 1 is ready. RSVD Reserved for future implementation. 3.1.17 Watch Dog Timer Load Register The MVME4100 provides a watch dog timer load register. Table 3-20 Watch Dog Timer Load Register Watch Dog Timer Control Register - 0xF200 0020 Field...

  • Page 44: Watch Dog Timer Resolution Register

    SYSRST System Reset. If cleared a board-level reset is generated when a time-out occurs. If set, a VMEbus SYSRST is generated when a time-out occurs. If MVME4100 is SYSCON then a local reset will also result in a VMEbus SYSRST.

  • Page 45: Watch Dog Timer Count Register

    32 ms 64 ms RSVD Reserved for future implementation. 3.1.20 Watch Dog Timer Count Register The MVME4100 provides a watch dog timer count register. Table 3-23 Watch Dog Timer Count Register Watch Dog Timer Counter Register - 0xF200 0026 15:0 Field...

  • Page 46: Pld Revision Register

    Register Descriptions 3.1.21 PLD Revision Register The MVME4100 provides a PLD revision register that can be read by the system software to determine the current revision of the timers/registers PLD. Table 3-24 PLD Revision Register PLD Revision Register - 0xF200 0030...

  • Page 47: Test Register 1

    TEST1 General purpose 32-bit R/W field. 3.1.24 Test Register 2 The MVME4100 provides a second 32-bit test register that reads back the complement of the data in Test Register 1. Table 3-27 Test Register 2 Test Register 2 - 0xF200 003C...

  • Page 48: External Timer Registers

    A write to this address will write the uncomplemented data to register TEST1. 3.1.25 External Timer Registers The MVME4100 provides a set of tick timer registers for access to the four external timers implemented in the timers/registers PLD. Note that these registers are 32-bit registers and are not byte writable.

  • Page 49: Control Registers

    ENINT Enable Interrupt. When the bit is set the interrupt is enabled. When the bit is cleared the interrupt is not enabled. CINT Clear Interrupt. INTS Interrupt Status. RSVD Reserved for future implementation. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 50: Compare Registers

    Tick Timer 2 Compare Register - 0xF202 0024 (32 bits) Tick Timer 3 Compare Register - 0xF202 0034 (32 bits) Tick Timer 4 Compare Register - 0xF202 0044 (32 bits) … Field Tick Timer Compare Value OPER RESET MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 51: Counter Register

    The VMEbus Status Register in the Tsi148 provides the VMEbus geographical address of the MVME4100. This register reflects the inverted states of the geographical address pins at the 5- row, 160-pin P1 connector. Applications not using the 5-row backplane can use the planar switch described in the MVME4100 Installation and Use manual to assign a geographical address.
  • Page 52 Register Descriptions MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 53: Programming Details

     MPC8548E Reset Configuration The MVME4100 supports the power-on reset (POR) pin sampling method for processor reset configuration. The states of the various configuration pins on the processor are sampled when reset is deasserted to determine the desired operating modes. Combinations of pull-up and pull-down resistors are used to set the options.

  • Page 54: Table 4-1 Mpc8548E Por Configuration Settings

    PCI-X mode configuration PCI mode EC_MDC Fixed TSEC 1 and 2 TSEC 1 and 2 in reduced mode width (RTBI or RGMII) configuration TSEC 1 and 2 in standard mode (TBI or GMII) MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 55 TSEC1_TCD[6:4] Fixed Boot ROM PCI1/PCI-X location DRR SDRAM PCI2 Serial Rapid IO PCI Express Local bus GPCM- 8-bit ROM Local bus GPCM - 16-bit ROM Local bus GPCM - 32-bit ROM MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 56 TSEC2 controller uses GMII protocol (RGMII if TSEC2 configured in reduced mode) TSEC2 controller uses TBI protocol (RTBI if TSEC2 configured in reduced mode) TSEC2_TXD[1, Fixed DDR DRAM Reserved TSEC2_RX_ER] type DDR1 Reserved DDR2 MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 57 TSEC4_TXD[2] Fixed SerDes enable SerDes interface is disabled SerDes interface is enabled LA[27] Fixed CPU boot CPU boot hold off mode configuration e500 core boots without waiting for configuration by an external master MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 58 Agent of a RapidIO; host PCI Express and PCI1/PCI-x Endpoint PCI Express; host RapidIO and PCI/PCI-X Reserved Agent PCI1/PCI-X and RapidIO; root complex PCI Express Agent PCI1/PCI-X; host RapidIO; root complex PCI Express Host processor/root complex MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 59 Debug info from the DDR SDRAM controller is driven on MSRCID and MDVAL pins MSRCID1 Fixed DDR debug Debug info on ECC pins configuration instead of normal ECC ECC pins function in normal mode MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 60: Mpc8548E Interrupt Controller

    Programming Details MPC8548E Interrupt Controller The MVME4100 uses the MPC8548E integrated programmable interrupt controller (PIC) to manage locally generated interrupts. Currently defined external interrupting devices and interrupt assignments, along with corresponding edge/levels and polarities, are shown in the following table.

  • Page 61: Local Bus Controller Chip Select Assignments

    1. Flash bank size determined by VPD flash packet. 2. Control/Status registers are byte read and write capable. 3. 32-bit timer registers are byte readable, but must be written as 32 bits. 4. MRAM is byte read and write capable. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 62: I2C Device Addresses

    C controller is used by the system software to read the contents of the various I C devices located on the MVME4100. The following table contains the I devices used for the MVME4100 and their assigned device addresses. Table 4-4 I2C Bus Device Addressing...

  • Page 63: Vpd Eeprom

    Programming Details VPD EEPROM The MVME4100 board provides an 8 KB dual address serial EEPROM containing Vital Product Data (VPD) configuration information specific to the MVME4100. Typical information that may be present in the EEPROM may include: manufacturer, board revision, build version, date of assembly, memory present, options present, L2 cache information, etc.

  • Page 64: Flash Memory

    Programming Details 4.10 Flash Memory The MVME4100 is designed to provide 128 MB of soldered-on NOR flash memory. Two +3.0 V devices are configured to operate in 16-bit mode to form a 32-bit flash bank. This flash bank is also the boot bank and is connected to LBC Chip Select 0 and 1. The NOR flash is accessed via the MPC8548E local bus.

  • Page 65: Pci Idsel And Interrupt Definition

    IRQ6 IRQ7 IRQ4 IRQ5 Primary 0b0_0011 PMC2 IRQ7 IRQ4 IRQ5 IRQ6 Secondary PCI2 0b0_0010 uPD720101 IRQ4 IRQ5 IRQ6 (PCI6520) Refer to the MPC8548E reference manual for additional details about the MPC8548E PIC operation. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 66: Pci Arbitration Assignments

    The integrated PCI/X arbiters internal to the PLX PCI6520 provide PCI arbitration for the MVME4100. The arbitration assignments on the MVME4100 are shown in the next table so that software may set arbiter priority assignments if necessary. Table 4-10 PCI Arbitration Assignments...

  • Page 67: Mram

    MRAM. 4.12.2 Real Time Clock The MVME4100 provides a battery backed up DS1375 RTC (Real TIme Clock) chip. The RTC chip provides time keeping and alarm interrupts. The RTC chip is an I2C device and is accessed via the I2C bus at address 0xD0.

  • Page 68: Lbc Timing Parameters

    NOR Flash NOR Flash NAND Flash MRAM UART Timers LBCTLD CSNT XACS SETA TRLX EHTR 4.12.5 USB Oscillator Configuration Software must configure the USB chip for the correct clock input of 48 MHz. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 69: Clock Distribution

    MPC9855 clock generator. Additional clocks required by individual devices are generated near the devices using individual oscillators. The following table lists the clocks required on the MVME4100 along with their frequency and source. Table 4-12 Clock Assignments...

  • Page 70: System Clock

    MPC8548E PIC timers which software can use as a known timing reference. 4.13.3 Local Bus Controller Clock Divisor The Local Bus Controller (LBC) clock output is connected to the PLD but is not used by the internal logic. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 71: Programmable Configuration Data

    Overview This appendix provides data and specifications pertaining to programmable parts used on the MVME4100. The board is shipped after the programmable parts have been programmed through ATE or boundary scan according to the In-Circuit Test specifications. Table A-1 Programmable Devices...

  • Page 72: Vital Product Data (Vpd) Introduction

    The firmware ignores the VPD contents and attempts to acquire information from other  sources. Some device drivers will not work.  Some diagnostic tests will fail.  The board will run much slower than usual.  MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 73: How To Fix Corrupted Vpd Information

    If you suspect that your board has problems, as a result of wrong VPD information, select SAFE mode by setting S1:1 ON and reboot the MVME4100. At this point, the firmware will ignore all SROM contents. Use SROM or the IBM command to change the VPD to the correct parameters.
  • Page 74 = 0xffffffff; for (index = 0; index < vpdSromSize; index++) dataByte = *pVpdBuffer++; for (dataBitValue = 0; dataBitValue < 8; dataBitValue++) msbDataBitValue = (crcValue >> 31) & 1; MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 75 >>= 1; crcValueFlipped = 0; for (index = 0; index < 32; index++) crcValueFlipped <<= 1; dataBitValue = crcValue & 1; crcValue >>= 1; crcValueFlipped += dataBitValue; crcValue = crcValueFlipped ^ 0xffffffff; return (crcValue); MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 76: Vpd Contents For Mvme4100 Boards

    # of Bytes BINARY Board Type: Processor Board BINARY Architecture Revision BINARY Board Build Revision BINARY Revision Reason Flags BINARY Product Identifier Packet Refer to Notes 1 and 2. BINARY # of bytes MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 77 Table A-3 Static VPD Contents (continued) Offset (HEX) Data (HEX) Field Type Description ASCII Product Identifier. Refer to Table A-4. BINARY Factory Assembly Number. Refer to Notes and 2. BINARY # of bytes MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 78 **Serial number to be filled in. Refer to Notes and 3. BINARY # of bytes ASCII Most significant serial number character Least significant serial number character BINARY External Processor Clock Frequency Packet BINARY # of bytes MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 79 Ethernet Controller 0 BINARY Ethernet MAC Address Packet BINARY # of bytes BINARY Six bytes containing the next Ethernet address. BINARY Ethernet Controller 1 BINARY Ethernet MAC Address Packet BINARY # of bytes MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 80 Ethernet MAC Address Packet BINARY # of bytes BINARY Six bytes containing the highest Ethernet address. BINARY Ethernet Controller 3 BINARY Processor Identifier Packet BINARY # of bytes ASCII Processor type Refer to Table A-4. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 81 Flash bank number BINARY Flash access speed in nanoseconds: 0x6E = 110 ns BINARY Total bank size [(1<<n)*256K bytes]: 0x09 = 128 MB BINARY Bank 2 Flash Memory Configuration Packet BINARY # of bytes MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 82 3. This data is not static. Each board's Serial Number packet must be unique. The board's serial number is obtained from the onboard serial number label. MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 83: Table A-4 Variable Vpd Contents

    Programmable Configuration Data The "xx" in Table A-4 at address 0x32 represents the assembly revision letter (A=41, B=42, etc.). Table A-4 Variable VPD Contents Offset (Hex) MVME4100-0171 MVME4100-0173 0106855E03x 0106855E04x MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 84 Programmable Configuration Data Table A-4 Variable VPD Contents (continued) Offset (Hex) MVME4100-0171 MVME4100-0173 0106855E03x 0106855E04x MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 85: Related Documentation

    The publications listed below are referenced in this manual. You can obtain electronic copies of Artesyn Embedded Technologies - Embedded Computing publications by contacting your local Artesyn sales office. For released products, you can also visit our Web site for the latest copies of our product documentation.
  • Page 86 Revised March 2004 8-bit Universal Bus Transceiver and Two 1-bit Bus Transceivers with Split LVTTL Port, Feedback Path, and 3-state Outputs Exar ST16C554/554D, ST68C554 Version 4.0.1 Quad UART with 16-Byte FIFO's June 2006 MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 87 MAX811/MAX812 19-0411 4-Pin μP Voltage Monitors Rev 3 With Manual Reset Input 3/99 MAX6649 Digital Temperature Sensor 19-2450 Rev 3 05/07 Tundra Semiconductor Corporation Tsi148 PCI/X-to-VME Bus Bridge User Manual FN 80A3020 MA001_08 MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)

  • Page 88: Related Specifications

    ANSI/VITA 32-2003 PCI-X on PMC ANSI/VITA 39-2003 PMC I/O Module (PIM) Draft Standard VITA 36 Draft Rev 0.1 July 19, 1999 Universal Serial Bus Universal Serial Bus Specification Revision 2.0 April 27, 2000 MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 89 Institute for Electrical and Electronics Engineers, Inc. IEEE Standard for a Common Mezzanine Card Family: CMC Family IEEE Std 1386 - 2001 IEEE Standard Physical and Environmental Layer for PCI Mezzanine Cards IEEE Std 1386.1 - 2001 (PMC) MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 90 Related Documentation MVME4100 Single Board Computer Programmer’s Reference (6806800H19C)
  • Page 92 Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners. © 2014 Artesyn Embedded Technologies, Inc.

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