Command Register 4 - National Instruments DAQ AT-MIO-16X User Manual

15 14
A4RCV A4DRV
MSB
7 6
EISA_DMA 0
© National Instruments Corporation
Command Register 2
Command Register 2 contains 15 bits that control AT-MIO-16X RTSI
bus transceivers, analog output configuration, and DMA Channels A
and B selection. Bits 8-15 of this register are cleared upon power up and
after a reset condition. Bits 0-7 of this register are undefined upon
power up and are not cleared after a reset condition. These bits should
be initialized through software.
Address: Base address + 02 (hex)
Type: Write-only
Word Size: 16-bit
Bit Map:
13 12
A2RCV A2DRV
5 4
DMACHBB2 DMACHBB1
Bit Name
15 A4RCV
14 A4DRV
Chapter 4
11 10
BIPDAC1 BIPDAC0
3 2
DMACHBB0 DMACHAB2
Description
RTSI A4 Receive—This bit controls the
signal source for the TMRTRIG* (Timer
Trigger) signal. The TMRTRIG* signal
updates the DACs in delayed update
mode. If A4RCV is set, pin A4 of the
RTSI switch drives the TMRTRIG*
signal. If A4RCV is cleared, the
TMRTRIG* signal is driven by the
EXTTMRTRG* signal from the I/O
connector.
RTSI A4 Drive—This bit controls the
driver that allows the OUT5 signal to
drive pin A4 of the RTSI switch. If
A4DRV is set, pin A4 of the RTSI switch
is driven by OUT5. If A4DRV is cleared,
pin A4 is not driven by OUT5, and it can
be driven by a signal on the RTSI bus.
4-9
Register Map and Descriptions
9 8
EXTREFDAC1 EXTREFDAC0
1 0
DMACHAB1 DMACHAB0
LSB
AT-MIO-16X User Manual