Page 1: User Manual
AT-MIO-16X User Manual Multifunction I/O Board for the PC AT/EISA October 1997 Edition Part Number 320640B-01 © Copyright 1992, 1997 National Instruments Corporation. All rights reserved.
Page 2 Korea 02 596 7456, Mexico 5 520 2635, Netherlands 0348 433466, Norway 32 84 84 00, Singapore 2265886, Spain 91 640 0085, Sweden 08 730 49 70, Switzerland 056 200 51 51, Taiwan 02 377 1200, United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 Tel: (512) 794-0100...
Page 3: Important Information
Important Information Warranty The AT-MIO-16X is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period.
Page 4: Table Of Contents
Conventions Used in This Manual... xvi Related Documentation... xvii Customer Communication ... xvii Chapter 1 Introduction About the AT-MIO-16X ... 1-1 Analog Input... 1-2 Analog Output ... 1-2 Digital and Timing I/O ... 1-3 What You Need to Get Started ... 1-3 Software Programming Choices ...
Page 5 EXTTMRTRIG* Signal ... 2-36 Counter Signal Connections ... 2-37 Field Wiring Considerations... 2-42 Cabling Considerations for the AT-MIO-16X with 50-Pin I/O Connector ... 2-43 Cabling Considerations for the AT-MIO-16X with 68-Pin I/O Connector ... 2-44 AT-MIO-16X User Manual © National Instruments Corporation...
Page 6 Chapter 4 Register Map and Descriptions Register Map... 4-1 Register Sizes ... 4-3 Register Description Format... 4-3 Configuration and Status Register Group... 4-4 Command Register 1... 4-5 Command Register 2... 4-9 © National Instruments Corporation Table of Contents AT-MIO-16X User Manual...
Page 7 Am9513A Status Register ... 4-67 Digital I/O Register Group... 4-68 Digital Input Register ... 4-69 Digital Output Register... 4-70 RTSI Switch Register Group ... 4-71 RTSI Switch Shift Register ... 4-72 RTSI Switch Strobe Register... 4-73 AT-MIO-16X User Manual viii © National Instruments Corporation...
Page 8 Chapter 5 Programming Register Programming Considerations... 5-1 Resource Allocation Considerations ... 5-1 Initializing the AT-MIO-16X ... 5-2 Initializing the Am9513A ... 5-3 Programming the Analog Input Circuitry... 5-5 Single Conversions Using the SCONVERT or EXTCONV* Signal ... 5-5 Generating a Single Conversion... 5-6 Reading a Single Conversion Result ...
Page 9 Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware ... 1-6 Figure 2-1. AT-MIO-16X with 50-Pin I/O Connector Parts Locator Diagram ... 2-1 Figure 2-2. AT-MIO-16X with 68-Pin I/O Connector Parts Locator Diagram ... 2-2 Figure 2-3.
Page 10 Figure 2-5. AT-MIO-16X 68-Pin I/O Connector ... 2-16 Figure 2-6. AT-MIO-16X PGIA ... 2-20 Figure 2-7. Differential Input Connections for Ground-Referenced Signals ... 2-23 Figure 2-8. Differential Input Connections for Nonreferenced Signals ... 2-24 Figure 2-9. Single-Ended Input Connections for Nonreferenced or Floating Signals ...
Page 11 AT-MIO-16X 50-Pin I/O Connector... B-2 Figure B-2. AT-MIO-16X 68-Pin I/O Connector... B-3 Tables Table 2-1. Default Settings of National Instruments Products for the PC... 2-4 Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space ... 2-5 Table 2-3.
Page 12 Equivalent Offset Errors in 16-Bit Systems ... A-3 Table A-2. Equivalent Gain Errors in 16-Bit Systems... A-4 Table A-3. Typical Multiple-Channel Scanning Settling Times ... A-5 Table B-1. Signal Connection Descriptions... B-4 © National Instruments Corporation xiii Table of Contents AT-MIO-16X User Manual...
Page 13: Appendix A Specifications
AT-MIO-16X and explains the operation of each functional unit making up the AT-MIO-16X. Chapter 4, Register Map and Descriptions, describes in detail the address and function of each of the AT-MIO-16X control and status registers. Chapter 5, Programming, contains programming instructions for operating the circuitry on the AT-MIO-16X.
Page 14: Appendix Camd Am9513A Data Sheet
Controller integrated circuit (Advanced Micro Devices, Inc.). This controller is used on the AT-MIO-16X. Appendix D, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products. The Glossary contains an alphabetical list and description of terms used in this manual, including abbreviations, acronyms, metric prefixes, mnemonics, and symbols.
Page 15: Customer Communication
AT-MIO-16X: • Customer Communication National Instruments want to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete.
Page 16: About The At-Mio-16X
16-bit accuracy at high gains when sampling multiple channels, National Instruments developed the NI-PGIA. The NI-PGIA, which is used on the AT-MIO-16X, is an instrumentation amplifier that settles to 16 bits in 40 s, even when the board is used at its highest gain of 100.
Page 17: Analog Input
Analog Input The AT-MIO-16X is a high-performance multifunction analog, digital, and timing I/O board for the PC. The AT-MIO-16X has a 10 sec, 16-bit, sampling ADC that can monitor a single input channel, or scan through the 16 single-ended or 8 differential channels (expandable with National Instruments multiplexing products) at a programmable gain of 1, 2, 5, 10, 20, 50, or 100 for unipolar or bipolar input ranges.
Page 18: Digital And Timing I/O
Detailed specifications for the AT-MIO-16X are listed in Appendix A, Specifications. What You Need to Get Started To set up and use your AT-MIO-16X Series board, you will need the following: © National Instruments Corporation One of the following boards:...
Page 19: Software Programming Choices
Chapter 1 Introduction Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use National Instruments application software, NI-DAQ, or register-level programming. National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI-DAQ driver software.
Page 20: Ni-Daq Driver Software
An example of a low-level function is writing directly to registers on the DAQ device. NI-DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak.
Page 21: Figure 1-1. The Relationship Between The Programming Environment
Chapter 1 Introduction Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write register-level software. Writing register-level programming software can be very time-consuming and inefficient, and is not recommended for most users. Even if you are an experienced register-level programmer, using...
Page 22: Optional Equipment
National Instruments catalogue or call the office nearest you. Unpacking Your AT-MIO-16X board is shipped in an antistatic package to prevent electrostatic damage to the board. Electrostatic discharge can damage several components on the board. To avoid such damage in handling the board, take the following precautions: •...
Page 23: Figure 2-1. At-Mio-16X With 50-Pin I/O Connector Parts Locator Diagram
AT-MIO-16X into the PC, signal connections to the AT-MIO-16X, and cable considerations. 1 Product Name, Assembly Number, and Revision Letter © National Instruments Corporation 2 Fuse Figure 2-1. AT-MIO-16X with 50-Pin I/O Connector Parts Locator Diagram Chapter 3 U112 4 Spare Fuse AT-MIO-16X User Manual...
Page 24: Board Configuration
DMA and interrupt channel selections, are determined by programming the individual registers in the AT-MIO-16X register set. The general location of the registers in the I/O space of the PC is determined by the base address selection, whereas the specific location of the registers within the register set is determined by the AT-MIO-16X decode circuitry.
Page 25: Base I/O Address Selection
Base I/O Address Selection The AT-MIO-16X is configured at the factory to a base I/O address of 220 hex. This base address setting is suitable for most systems. However, if your system has other hardware at this base I/O address, you must change either the AT-MIO-16X base address DIP switch or the other hardware base address to avoid a conflict.
Page 26: Table 2-1. Default Settings Of National Instruments Products For The Pc
(LSBs) of the address (A4 through A0) used by the AT-MIO-16X circuitry to decode the individual register selections. The don’t care bits indicate the size of the register space. In this case, the AT-MIO-16X uses I/O address hex 220 through hex 23F in the factory-default setting. Note:...
Page 27: Table 2-2. Switch Settings With Corresponding Base I/O Address And
Table 2-1. Default Settings of National Instruments Products for the PC (Continued) AT-MIO-64F-5 GPIB-PCII GPIB-PCIIA GPIB-PCIII Lab-PC PC-DIO-24 PC-DIO-96 PC-LPM-16 PC-TIO-10 * These settings are software configurable and are disabled at startup time. © National Instruments Corporation Board Channel None*...
Page 28 Chapter 2 Configuration and Installation AT-MIO-16X User Manual Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space (Continued) Switch Setting Base I/O Base I/O Address Space Address (hex) Used (hex) 1C0 - 1DF 1E0 - 1FF...
Page 29: Interrupt And Dma Channel Selection
Interrupt and DMA Channel Selection The base I/O address selection is the only resource on the AT-MIO-16X board that must be set manually before the board is placed into the PC. The interrupt level and DMA channels used by the AT-MIO-16X are selected via registers in the AT-MIO-16X register set.
Page 30: Diff Input (Eight Channels)
This is the recommended configuration. With this input configuration, the AT-MIO-16X can monitor up to eight different analog input signals. This configuration is selected via software. See the configuration memory register and Table 4-9 in Chapter 4, Register Map and Descriptions.
Page 31: Rse Input (16 Channels)
NRSE input means that all input signals are referenced to the same common-mode voltage, but this common-mode voltage can float with respect to the analog ground of the AT-MIO-16X board. This common-mode voltage is subsequently subtracted from the signals by the input PGIA. This configuration is useful when measuring ground-referenced signal sources.
Page 32: Input Polarity And Input Range
AT-MIO-16X analog-to-digital converter (ADC) can accommodate. The AT-MIO-16X board has gains of 1, 2, 5, 10, 20, 50, and 100 and is suited for a wide variety of signal levels. With the proper gain setting, the full resolution of the ADC can be used to measure the input signal.
Page 33: Analog Output Configuration
Analog Output Reference Selection Each DAC can be connected to the AT-MIO-16X internal reference of 10 V or to the external reference signal connected to the EXTREF pin on the I/O connector. This signal applied to EXTREF must be between –18 and +18 V.
Page 34: Analog Output Polarity Selection
0 to 65,535 decimal (0 to FFFF hex). Digital I/O Configuration The AT-MIO-16X contains eight lines of digital I/O for general-purpose use. The eight digital I/O lines supplied are configured as two 4-bit ports. Each port can be individually configured through programming of a register in the board register set as either input or output.
Page 35: Hardware Installation
2. Remove the top cover or access port to the I/O channel. 3. Remove the expansion slot cover on the back panel of the 4. Insert the AT-MIO-16X into a 16-bit slot. Do not force the board 5. Attach a RTSI cable to the RTSI connectors to connect AT Series 6.
Page 36: Signal Connections
Caution: Connections that exceed any of the maximum ratings of input or output signals on the AT-MIO-16X can result in damage to the AT-MIO-16X board and to the PC. Maximum input ratings for each signal are given in this chapter under the discussion of that signal. National Instruments is not liable for any damages resulting from such signal connections.
Page 37: Figure 2-4. At-Mio-16X 50-Pin I/O Connector
Figure 2-4 shows the pin assignments for the AT-MIO-16X 50-pin I/O connector. © National Instruments Corporation Chapter 2 AI GND ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 AI SENSE DAC1 OUT AO GND ADIO0 ADIO1 ADIO2 ADIO3 DIG GND...
Page 38: Figure 2-5. At-Mio-16X 68-Pin I/O Connector
Chapter 2 Configuration and Installation Figure 2-5 shows the pin assignments for the AT-MIO-16X 68-pin I/O connector. AT-MIO-16X User Manual ACH0 ACH8 AIGND ACH1 ACH9 AIGND ACH2 ACH10 AIGND ACH3 ACH11 AIGND AISENSE ACH4 AIGND ACH12 ACH13 ACH5 ACH6 AIGND...
Page 39: Signal Connection Descriptions
ADIO<0..3> DIG GND BDIO<0..3> DIG GND +5 V DIG GND © National Instruments Corporation Chapter 2 Descriptions Analog Input Ground—These pins are the reference point for single-ended measurements and the bias current return point for differential measurements. Analog Input Channels 0 through 15—In differential mode, the input is configured for up to eight channels.
Page 40 SOURCE5 DIG GND GATE5 DIG GND AT-MIO-16X User Manual Descriptions Scan Clock—This pin pulses once for each A/D conversion in the scanning modes. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal.
Page 41: Analog Input Signal Connections
Analog Input Signal Connections AI GND is an analog input common signal that is routed directly to the ground tie point on the AT-MIO-16X. These pins can be used for a general analog power ground tie point to the AT-MIO-16X if necessary.
Page 42: Figure 2-6. At-Mio-16X Pgia
AT-MIO-16X board. Signals are routed to the positive (+) and negative (–) inputs of the PGIA through input multiplexers on the AT-MIO-16X. The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier.
Page 43: Types Of Signal Sources
An instrument or device that provides an isolated output falls into the floating signal source category. The ground reference of a floating signal must be tied to the AT-MIO-16X analog input ground in order to establish a local or onboard reference for the signal.
Page 44: Differential Connection Considerations (Diff Input Configuration)
Differential connections are those in which each AT-MIO-16X analog input signal has its own reference signal or signal return path. These connections are available when the AT-MIO-16X is configured in the DIFF input mode. Each input signal is tied to the positive (+) input of the PGIA;...
Page 45: Differential Connections For Ground-Referenced Signal Sources
Signal Sources Figure 2-7 shows how to connect a ground-referenced signal source to an AT-MIO-16X board configured in the DIFF input mode. The AT-MIO-16X analog input circuitry must be configured for DIFF input to make these types of connections. Configuration instructions are included in Chapter 4, Register Map and Descriptions.
Page 46: Differential Connections For Nonreferenced Or Floating Signal Sources
Floating Signal Sources Figure 2-8 shows how to connect a floating signal source to an AT-MIO-16X board configured in the DIFF input mode. The AT-MIO-16X analog input circuitry must be configured for DIFF input to make these types of connections. Configuration instructions are included in Chapter 4, Register Map and Descriptions.
Page 47 1-k source will produce no more than 1 V of input offset (0.33 LSB at a gain of 100, bipolar range). If the source is AC coupled, then the resulting DC offset is less than 1 nA times the sum of the two bias © National Instruments Corporation 2-25 AT-MIO-16X User Manual...
Page 48: Single-Ended Connection Considerations
AT-MIO-16X should not supply one. If using the AT-MIO-16X with a 50-pin I/O connector in single-ended configurations, more electrostatic and magnetic noise couples into the signal connections than in differential configurations. Moreover, the amount of coupling varies among channels, especially if a ribbon cable is used.
Page 49: Single-Ended Connections For Floating Signal Sources (Rse Configuration)
Figure 2-9 shows how to connect a floating signal source to an AT-MIO-16X board configured for single-ended input. The AT-MIO-16X analog input circuitry must be configured for RSE input to make these types of connections. Configuration instructions are included in Chapter 4, Register Map and Descriptions.
Page 50: Single-Ended Connections For Grounded Signal Sources (Nrse Configuration)
The signal is connected to the positive (+) input of the AT-MIO-16X PGIA and the signal local ground reference is connected to the negative (–) input of the AT-MIO-16X PGIA. The ground point of the signal should therefore be connected to the AI SENSE pin.
Page 51: Common-Mode Signal Rejection Considerations
Figures 2-7 and 2-8, located earlier in this chapter, show connections for signal sources that are already referenced to some ground point with respect to the AT-MIO-16X. In these cases, the PGIA can reject any voltage caused by ground potential differences between the signal source and the AT-MIO-16X.
Page 52: Figure 2-11. Analog Output Connections
AO GND is the ground reference point for both analog output channels and for the external reference signal. Figure 2-11 shows how to make analog output connections and the external reference input connection to the AT-MIO-16X board. External Reference V ref...
Page 53: Digital I/O Signal Connections
With these specifications, each digital output line can drive 11 standard TTL loads and over 50 LS TTL loads. Figure 2-12 depicts signal connections for three typical digital I/O applications. © National Instruments Corporation input logic high voltage input logic low voltage input current load,...
Page 54: Power Connections
Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2-12. Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2-12.
Page 55: Timing Connections For Data Acquisition And Analog Output
Under no circumstances should these +5-V power pins be directly connected to analog or digital ground or to any other voltage source on the AT-MIO-16X or any other device. Doing so can damage the AT-MIO-16X and the PC. National Instruments is not liable for damages resulting from such a connection.
Page 56: Extconv* Signal
Note: EXTCONV* and the output of Counter 3 of the Am9513A are physically connected together on the AT-MIO-16X. If Counter 3 is used in an application, the EXTCONV* signal must be left undriven. Conversely, if EXTCONV* is used in an application, Counter 3 must be disabled.
Page 57: Exttrig* Signal
First A/D conversion starts within 1 sample interval from this point Figure 2-15. EXTTRIG* Signal Timing The EXTTRIG* pin is also used to initiate AT-MIO-16X pretriggered data acquisition operations. In pretriggered mode, data is acquired after the first falling edge trigger is received, but no sample counting occurs until after a second falling edge trigger is applied to the EXTTRIG* pin.
Page 58: Extgate* Signal
If EXTGATE* is high, conversions take place if programmed and otherwise enabled. EXTTMRTRIG* Signal The analog output DACs on the AT-MIO-16X can be updated using either internal or external signals in posted update mode. The DACs can be updated externally by using the EXTTMRTRIG* signal from the I/O connector.
Page 59: Counter Signal Connections
Counter operation can be gated on and off during event counting. Figure 2-17 shows connections for a typical event-counting operation in which a switch is used to gate the counter on and off. © National Instruments Corporation 2-37...
Page 60: Figure 2-17. Event-Counting Application With External Switch Gating
If the counter is programmed to count an internal timebase, then the time lapse since receiving the edge is equal to the counter value multiplied by the timebase period. AT-MIO-16X User Manual +5 V 4.7 k...
Page 61: Figure 2-18. Frequency Measurement Application
Two or more counters can be concatenated by tying the OUT signal from one counter to the SOURCE signal of another counter. The counters can then be treated as one 32-bit or 48-bit counter for most counting applications. © National Instruments Corporation 2-39 AT-MIO-16X User Manual...
Page 62 Figure 2-19 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the Am9513A. AT-MIO-16X User Manual resistor. The input and output ratings and input logic high voltage input logic low voltage...
Page 63: Figure 2-19. General-Purpose Timing Signals
In addition to the signals applied to the SOURCE and GATE inputs, the Am9513A generates six internal timebase clocks from the clock signal supplied by the AT-MIO-16X. The base clock signal is selected by a © National Instruments Corporation t gsu...
Page 64: Field Wiring Considerations
Chapter 2 Configuration and Installation register in the AT-MIO-16X register set and then divided by 10. The default value is 1 MHz into the Am9513A (10-MHz clock signal on the AT-MIO-16X). The six internal timebase clocks can be used as counting sources, and these clocks have a maximum skew of 75 nsec between them.
Page 65: Cabling Considerations For The At-Mio-16X With 50-Pin I/O Connector
Separate AT-MIO-16X signal lines from high-current or high-voltage lines. These lines are capable of inducing currents in or voltages on the AT-MIO-16X signal lines if they run in parallel paths at a close distance. Reduce the magnetic coupling between lines by separating them by a reasonable distance if they run in parallel, or by running the lines at right angles to each other.
Page 66: Cabling Considerations For The At-Mio-16X With 68-Pin I/O Connector
Cabling Considerations for the AT-MIO-16X with 68-Pin I/O Connector National Instruments has a 68-pin mating connector and shell kit you can use with the AT-MIO-16X board. In making your own cabling, you may decide to shield your cables. The following guidelines may help: •...
Page 67: Theory Of Operation
Theory of Operation This chapter contains a functional overview of the AT-MIO-16X and explains the operation of each functional unit making up the AT-MIO-16X. Functional Overview The block diagram in Figure 3-1 is a functional overview of the AT-MIO-16X board.
Page 68: Pc I/O Channel Interface Circuitry
PC I/O Channel Interface Circuitry The AT-MIO-16X board is a full-size 16-bit PC I/O channel adapter. The PC I/O channel consists of a 24-bit address bus, a 16-bit data bus, a DMA arbitration bus, interrupt lines, and several control and support signals.
Page 69: Figure 3-2. Pc I/O Channel Interface Circuitry Block Diagram
AT-MIO-16X multiple-function circuitry. The PC I/O channel has 24 address lines; the AT-MIO-16X uses 10 of these lines to decode the board address. Therefore, the board address range is 000 to 3FF hex. SA5 through SA9 are used to generate the board enable signal.
Page 70 Theory of Operation conflicts with any other equipment in your PC, you must change the base address of the AT-MIO-16X or of the other device. See Chapter 2, Configuration and Installation, for more information. The PC I/O channel interface timing signals are used to generate read-and-write signals and to define the transfer cycle size.
Page 71: Analog Input And Data Acquisition Circuitry
DMA transfer. These DMA channels are selectable from one of the registers in the AT-MIO-16X register set. Analog Input and Data Acquisition Circuitry The AT-MIO-16X handles 16 channels of analog input with software-programmable configuration and 16-bit A/D conversion. In...
Page 72: Analog Input Circuitry
The ADC has two input modes that are software selectable on the AT-MIO-16X board on a per channel basis: –10 to +10 V, or 0 to +10 V. The ADC on the AT-MIO-16X is guaranteed to convert at a rate of at least 100 ksamples/sec.
Page 73: Pgia
The PGIA also applies gain to the input signal, amplifying an input analog signal before sampling and conversion to increase measurement resolution and accuracy. Software-selectable gains of 1, 2, 5, 10, 20, 50, and 100 are available through the AT-MIO-16X PGIA on a per channel basis. ADC FIFO Buffer When an A/D conversion is complete, the ADC circuitry shifts the result into the ADC FIFO buffer.
Page 74: Data Acquisition Timing Circuitry
This section details the different methods of acquiring A/D data from a single channel or multiple channels. Prior to any of these operations, the channel, gain, mode, and range settings must be configured. This is accomplished through writing to a register in the AT-MIO-16X register set. Single-Read Timing...
Page 75: Single-Channel Data Acquisition Timing
A/D conversions) carefully timed. The data acquisition timing circuitry consists of various clocks and timing signals. Three types of data acquisition are available with the AT-MIO-16X board: single-channel data acquisition, multiple-channel data acquisition with continuous scanning, and multiple-channel data acquisition with interval scanning.
Page 76: Figure 3-5. Single-Channel Posttrigger Data Acquisition Timing
AT-MIO-16X register set. The data acquisition process can be initiated via software or by applying an active low pulse to the EXTTRIG* input on the AT-MIO-16X I/O connector. Figure 3-5 shows the timing of a typical single-channel data acquisition sequence. Trigger*...
Page 77: Figure 3-6. Single-Channel Pretrigger Data Acquisition Timing
For posttrigger sequences, © National Instruments Corporation Figure 3-6. Single-Channel Pretrigger Data Acquisition Timing 3-11...
Page 78: Multiple-Channel Data Acquisition
Counter 1 of the Am9513A Counter/Timer. With this method, the location pointer can be incremented once every N A/D conversions so that N conversions can be performed on a single-channel configuration selection before switching to the next configuration memory selection. AT-MIO-16X User Manual 3-12 © National Instruments Corporation...
Page 79: Continuous Scanning Data Acquisition Timing
Scanning is similar to the single-channel acquisition in the programming of both the sample-interval counter and the sample counter. Scanning data acquisition is enabled through a register in the AT-MIO-16X register set. Figure 3-7 shows the timing for a continuous scanning data acquisition sequence. Trigger*...
Page 80: Interval Scanning Data Acquisition Timing
Interval-scanning monitors the N channels every scan interval, so the effective channel conversion interval is equal to the interval between scans. AT-MIO-16X User Manual Figure 3-8. Interval Scanning Posttrigger Data Acquisition Timing 3-14 © National Instruments Corporation...
Page 81: Data Acquisition Rates
AT-MIO-16X in scanning modes. Analog Output and Timing Circuitry The AT-MIO-16X has two channels of 16-bit D/A output. Unipolar or bipolar output and internal or external reference voltage selection are available with each analog output channel through a register in the AT-MIO-16X register set.
Page 82: Analog Output Circuitry
The DAC in each analog output channel generates a voltage proportional to the input voltage reference (V digital code loaded into the DAC. Each DAC can be loaded with a 16-bit digital code by writing to registers on the AT-MIO-16X board. AT-MIO-16X User Manual REF Selection...
Page 83: Analog Output Configuration
Analog Output Configuration The DAC output op-amps can be configured through one of the AT-MIO-16X registers to generate either a unipolar voltage output or a bipolar voltage output range. A unipolar output has an output voltage range of 0 to +V A bipolar output has an output voltage range of –V...
Page 84: Dac Waveform Circuitry And Timing
AT-MIO-16X board can be recalibrated without external hardware at any time under any number of different operating conditions in order to remove errors caused by temperature drift and time. The AT-MIO-16X is factory calibrated in both unipolar and bipolar modes, and these values are also permanently stored in the EEPROM.
Page 85: Figure 3-10. Analog Output Waveform Circuitry
DACs in the immediate update mode is the local latch. The path that the data takes to the DACs is determined by the DAC mode enabled through a register in the AT-MIO-16X register set. The DAC FIFO and RTSI latch are used for posted updating of the DACs.
Page 86: Dac Waveform Timing Circuitry
Am9513A Counter/Timer, it can be supplied from the EXTTMRTRIG* signal at the I/O connector, or it can be obtained by accessing a register in the AT-MIO-16X register set. In the posted update mode, requests for writes to the DAC are generated...
Page 87: Figure 3-12. Analog Output Waveform Circuitry
DAC FIFOs. This condition can be prevented in the cyclic mode where the buffer resides wholly in the DAC FIFO and is cycled through to generate a © National Instruments Corporation 3-21 AT-MIO-16X User Manual...
Page 88: Fifo Continuous Cyclic Waveform Generation
Retransmit. This is a signal generated by the hardware in cyclic mode to trigger the DAC FIFO to retransmit its buffer. The CYCLICSTOP signal is programmable through a register in the AT-MIO-16X register set. If this bit is cleared, the DAC FIFO hardware runs ad infinitum or until the timer update pulse triggering is disabled.
Page 89: Fifo Programmed Cyclic Waveform Generation
DAC FIFO. Figure 3-15 shows the operation of this mode and the resulting waveform. DACFIFORT* CTR 1 CTR 1 Output CTR 2 Terminal Count © National Instruments Corporation Figure 3-14. FIFO Programmed Cyclic Waveform Timing Figure 3-15. FIFO Pulsed Waveform Generation Timing 3-23 Chapter 3 Theory of Operation...
Page 90: Digital I/O Circuitry
CYCLICSTOP bit is set. Digital I/O Circuitry The AT-MIO-16X has eight digital I/O lines. These eight digital I/O lines are divided into two ports of four lines each and are located at pins ADIO<3..0> and BDIO<3..0> on the I/O connector. Figure 3-16 shows a block diagram of the digital I/O circuitry.
Page 91: Timing I/O Circuitry
The external strobe signal EXTSTROBE*, shown in Figure 3-16, is a general-purpose strobe signal. Writing to an address location on the AT-MIO-16X board generates an active low 500-nsec pulse on this output pin. EXTSTROBE* is not necessarily part of the digital I/O circuitry but is shown here because it can be used to latch digital output from the AT-MIO-16X into an external device.
Page 92: Figure 3-17. Timing I/O Circuitry Block Diagram
These timebases can be used as clocks by the counter/timers and by the frequency output channel. When BRDCLK is 10 MHz, the six internal timebases normally used for AT-MIO-16X timing functions are 5 MHz, 1 MHz, 100 kHz, 10 kHz, 1 kHz, and 100 Hz.
Page 93: Figure 3-18. Counter Block Diagram
Terminal count is often referred to as TC. A counter reaches TC when it counts up or down and rolls over. In many © National Instruments Corporation SOURCE Counter GATE Figure 3-18.
Page 94 The GATE and OUT pins for Counters 1, 2, and 5 and SOURCE pins for Counters 1 and 5 of the onboard Am9513A are located on the AT-MIO-16X I/O connector. A falling edge signal on the EXTTRIG* pin of the I/O connector or writing to the STARTDAQ register during...
Page 95: Rtsi Bus Interface Circuitry
FOUT pin. RTSI Bus Interface Circuitry The AT-MIO-16X is interfaced to the National Instruments RTSI bus. The RTSI bus has seven trigger lines and a system clock line. All National Instruments AT Series boards with RTSI bus connectors can be wired together inside the PC and share these signals.
Page 96 RTSI bus. The RTSI switch is programmed via its chip select and data inputs. On the AT-MIO-16X board, nine signals are connected to pins A<6..0> of the RTSI switch with the aid of additional drivers. The signals GATE1, OUT1, OUT2, SOURCE5, OUT5, and FOUT are shared with the AT-MIO-16X I/O connector and Am9513A Counter/Timer.
Page 97: Register Map And Descriptions
Register Map The register map for the AT-MIO-16X is shown in Table 4-1. This table gives the register name, the register offset address, the type of the register (read-only, write-only, or read-and-write) and the size of the register in bits.
Page 98 Chapter 4 Register Map and Descriptions Table 4-1. AT-MIO-16X Register Map (Continued) Register Name Analog Output Register Group DAC0 Register DAC1 Register ADC Event Strobe Register Group CONFIGMEMCLR Register CONFIGMEMLD Register DAQ Clear Register DAQ Start Register Single Conversion Register...
Page 99: Register Sizes
Register Description Format The remainder of this register description chapter discusses each of the AT-MIO-16X registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register. The individual register description gives the address, type, word size, and bit map of the register, followed by a description of each bit.
Page 100: Configuration And Status Register Group
Configuration and Status Register Group The six registers making up the Configuration and Status Register Group allow general control and monitoring of the AT-MIO-16X hardware. Command Registers 1, 2, 3, and 4 contain bits that control operation of several different pieces of the AT-MIO-16X hardware.
Page 101: Command Register 3
Command Register 1 Command Register 1 contains 11 bits that control AT-MIO-16X serial device access, and data acquisition mode selection. The contents of this register are not defined upon power up and are not cleared after a reset condition. This register should be initialized through software.
Page 102 RETRIG_DIS Retrigger Disable—This bit controls retriggering of the AT-MIO-16X data acquisition circuitry. When RETRIG_DIS is set, retriggering of the data acquisition circuitry is inhibited until the end of the previous operation is acknowledged by clearing the DAQPROG bit in Status Register 0.
Page 103 © National Instruments Corporation Chapter 4 thereby initiating a data acquisition operation. If DAQEN is cleared, software and hardware triggers have no effect. SCANEN Scan Enable—This bit controls multiple-channel scanning during data acquisition. If SCANEN is set and DAQEN is also set, alternate analog...
Page 104 Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual concatenated with Counter 5 to control conversion counting. A 16-bit count mode can be used if the number of A/D sample conversions to be performed is less than 65,537. A 32-bit count mode...
Page 105: Command Register 4
Command Register 2 Command Register 2 contains 15 bits that control AT-MIO-16X RTSI bus transceivers, analog output configuration, and DMA Channels A and B selection. Bits 8-15 of this register are cleared upon power up and after a reset condition. Bits 0-7 of this register are undefined upon power up and are not cleared after a reset condition.
Page 106 Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual A2RCV RTSI A2 Receive—This bit controls the driver that allows the GATE1 signal to be driven from pin A2 of the RTSI switch. If A2RCV is set, pin A2 of the RTSI switch drives the GATE1 signal.
Page 107 EISA_DMA is clear, single transfer DMA mode is used. If EISA_DMA is set, demand-mode DMA is used. This bit should only be set if the AT-MIO-16X is installed in an EISA-type computer. Reserved—This bit must always be set to zero.
Page 108: Table 4-2. Dma Channel Selection
Chapter 4 Register Map and Descriptions Bit Pattern AT-MIO-16X User Manual Table 4-2. DMA Channel Selection Effect Primary DMA Channel Selected (A) DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 No effect DMA Channel 5 DMA Channel 6...
Page 109 Address: Type: Word Size: Bit Map: ADCDSP DIOPBEN DIOPAEN DMACHB ADCREQ DAC1REQ © National Instruments Corporation Base address + 04 (hex) Write-only 16-bit DMATCINT DACCMPLINT DAC0REQ DRVAIS Name Description ADCDSP ADC DSP Link Enable—This bit controls the serial link from the A/D converter to the AT-DSP2200.
Page 110 Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual DIOPAEN Digital I/O Port A Enable—This bit controls the 4-bit digital port A. If DIOPAEN is set, the Digital Output Register drives the DIO<4..1> digital lines at the I/O connector. If DIOPAEN is cleared, the Digital Output Register drivers are set to a high-impedance state;...
Page 111 OVERRUN or OVERFLOW. I/O_INT Input/Output Interrupt Enable—This bit, along with the appropriate mode bits, enables and disables I/O interrupts generated from the AT-MIO-16X. To select a specific mode, refer to Table 4-3 for available modes and associated bit patterns. DMACHA DMA Channel A Enable—This bit...
Page 112: Table 4-3. Dma And Interrupt Modes
Channel A and Channel B to DAC1 (double-buffered) Channel A and Channel B to DAC0 and DAC1 (sync double-channel) Channel A and Channel B from ADC (double-buffered) AT-MIO-16X User Manual ADCREQ ADC Request Enable—This bit controls DMA requesting and interrupt generation from an A/D conversion.
Page 113 Channel B to DAC0 and DAC1 (interleaved) with ADC interrupt Channel B from ADC with timer interrupt Channels A and B to DACs 0 and 1 (double-buffered) with ADC interrupt © National Instruments Corporation Chapter 4 Register Map and Descriptions Mode Description...
Page 114 Channel A to DAC0 and Channel B from ADC Channel A to DAC1 and Channel B from ADC Channel A to DAC0 and DAC1 (interleaved) and Channel B from ADC AT-MIO-16X User Manual Mode Description DAC1REQ DAC 1 Request Enable—This bit controls DMA requesting and interrupt generation from D/A updates.
Page 115: Table 4-4. Interrupt Level Selection
NRSE input configuration, and is not driven otherwise. INTCHB<2..0> Interrupt Channel Select—These bits select the interrupt channel available for use by the AT-MIO-16X. See Table 4-4. Table 4-4. Interrupt Level Selection Bit Pattern 4-19 Chapter 4...
Page 116 Chapter 4 Register Map and Descriptions Command Register 4 Command Register 4 contains 16 bits that control the AT-MIO-16X board clock selection, serial DAC link over the RTSI bus, DAC mode selection, and miscellaneous configuration bits. Bits 8-15 of this register are cleared upon power up or following a reset condition.
Page 117: Table 4-5. Board And Rtsi Clock Selection
11-8 © National Instruments Corporation Table 4-5. Board and RTSI Clock Selection Bit Pattern RTSI Clock No connection Internal, 10 MHz Driven onto board clock DAC1DSP DAC 1 DSP Link Enable—This bit controls the serial link from the AT-DSP2200 to DAC 1 of the analog output section.
Page 118: Table 4-6. Analog Output Waveform Modes
Chapter 4 Register Map and Descriptions Waveform Mode AT-MIO-16X User Manual update. If DACMB3 is set, the circuitry will determine whether to perform one read or two reads from the DAC FIFO depending on the data in the FIFO. See Table 4-6 for available modes and bit patterns.
Page 119 © National Instruments Corporation Chapter 4 Values can be directly written to the DAC, but not through the DAC FIFO. If DACGATE is cleared, updating of and writing to the DACs proceeds normally. DB_DIS Double Buffering Disable—This bit controls the updating of the DACs. If...
Page 120 EXTTRIG_DIS External Trigger Disable—This bit gates the EXTTRIG* signal from the I/O connector. If EXTTRIG_DIS is set, triggers from EXTTRIG* are ignored by the AT-MIO-16X circuitry. If this bit is cleared, triggers from the EXTTRIG* signal are able to initiate data acquisition sequences.
Page 121: Status Register 1
Status Register 1 Status Register 1 contains 16 bits of AT-MIO-16X hardware status information, including interrupt, analog input status, analog output status, and data acquisition progress. Address: Type: Word Size: Bit Map: DAQCOMP DAQPROG ADCFIFOHF* TMRREQ DACCOMP DAQFIFOFF* © National Instruments Corporation...
Page 122 Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual data acquisition operation has completed. ADCFIFOHF* ADC FIFO Half-Full Flag—This bit reflects the state of the ADC IFO. If the appropriate conversion interrupts are enabled, see Table 4-3, and ADCFIFOHF* is clear, the current...
Page 123 © National Instruments Corporation Chapter 4 until cleared by strobing the DMATCB Clear Register. OVERFLOW Overflow—This bit indicates whether the ADC FIFO has overflowed during a sample run. OVERFLOW is an error condition that occurs if the FIFO fills up with A/D conversion data and A/D conversions continue.
Page 124 Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual I/O modes, TMRREQ must be cleared by strobing the TMRREQ Clear Register. DACCOMP DAC Sequence Complete—This bit reflects the status of the DAC sequence termination circuitry. When the DAC sequence has normally completed, or ended on an error condition, the DACCOMP bit is set.
Page 125 © National Instruments Corporation Chapter 4 DACs, and DACCOMP is set, this is an error condition and should be handled appropriately. If DACFIFOEF* is set, then the DAC FIFO has at least one remaining point to be transferred. EEPROMDATA EEPROM Data—This bit reflects the...
Page 126: Status Register 2
Chapter 4 Register Map and Descriptions Status Register 2 Status Register 2 contains 1 bit of AT-MIO-16X hardware status information for monitoring the status of the A/D conversion. Address: Type: Word Size: Bit Map: 15-1 AT-MIO-16X User Manual Base address + 1A (hex)
Page 127: Analog Input Register Group
ADC FIFO. Reading from the ADC FIFO Register location transfers data from the AT-MIO-16X ADC FIFO buffer to the PC. Writing to the CONFIGMEM Register location sets up channel configuration information for the analog input section.
Page 128: Adc Fifo Register
ADC is configured. The bit pattern returned for either format is given as follows: Address: Type: Word Size: Bit Map: 15-0 AT-MIO-16X User Manual Base address + 00 (hex) Read-only 16-bit Name Description D<15..0> Local data bus bits. When the ADC FIFO is addressed, these bits are the result of a 16-bit ADC conversion.
Page 129: Table 4-7. Straight Binary Mode A/D Conversion Values
+10 V input range. To convert from the ADC FIFO value to the input voltage measured, use the following formula: © National Instruments Corporation (0x8000 to 0x7FFF) when the ADC is in bipolar mode. Table 4-7. Straight Binary Mode A/D Conversion Values...
Page 130: Table 4-8. Two's Complement Mode A/D Conversion Values
Chapter 4 Register Map and Descriptions To convert from the ADC FIFO value to the input voltage measured, use the following formula: AT-MIO-16X User Manual Table 4-8. Two’s Complement Mode A/D Conversion Values Input Voltage (Gain = 1) Decimal –10.0 V –32,768...
Page 131: Configmem Register
512 channel configuration settings for use in scanning sequences. Address: Type: Word Size: Bit Map: CHAN_SE CHAN_AIS CHAN_CAL CHANSEL1 CHANSEL0 CH_GAIN2 © National Instruments Corporation Base address + 08 (hex) Write-only 16-bit CHAN_BIP CH_GAIN1 CH_GAIN0 Name Description CHAN_SE Channel Single-Ended—This bit configures the analog input section for single-ended or differential mode.
Page 132 Chapter 4 Register Map and Descriptions 11-10 AT-MIO-16X User Manual CHAN_BIP Channel Bipolar—This bit configures the ADC for unipolar or bipolar mode. When CHAN_BIP is clear, the ADC is configured for unipolar operation and values read from the ADC FIFO are in straight binary format.
Page 133 © National Instruments Corporation Selected Analog Input Channels Single-Ended CHANSEL<3..0> 0111 1000 1001 1010 1011 1100 1101 1110 1111 CH_GAIN<2..0>Channel Gain Select–These three bits control the gain setting of the input PGIA for the selected channel. The following gains can be selected on the AT-MIO-16X: CH_GAIN<2..0>...
Page 134 Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual CH_GAIN<2..0> CHAN_LAST Channel Last—This bit should be set in the last entry of the scan sequence loaded into the channel configuration memory. More than one occurrence of the CHAN_LAST bit is possible in the configuration memory list for the interval-scanning mode.
Page 135: Table 4-9. Input Configuration
A strobe of the CONFIGMEMLD Register is still necessary to load the first value in the memory. © National Instruments Corporation Table 4-9. Input Configuration Bit Map PGIA (+)
Page 136 In the single-channel data acquisition mode, only one value should be written and loaded into the channel configuration register. AT-MIO-16X User Manual 4-40 © National Instruments Corporation...
Page 137: Analog Output Register Group
V The digital code in the above formula is a decimal value ranging from 0 to 65,535. © National Instruments Corporation * (digital code) 65,536 is the reference voltage applied to the analog output channel.
Page 138: Table 4-10. Analog Output Voltage Versus Digital Code (Unipolar Mode)
V channel. The digital code in the preceding formula is a decimal value ranging from –32,768 to +32,767. AT-MIO-16X User Manual Table 4-10. Analog Output Voltage Versus Digital Code (Unipolar Mode) Digital Code Decimal...
Page 139 Table 4-11. Analog Output Voltage Versus Digital Code (Bipolar Mode) (Continued) Bit descriptions for the registers making up the Analog Output Register Group are given on the following pages. © National Instruments Corporation Digital Code Decimal 16,384 4000 32,767 7FFF...
Page 140: Dac0 Register
DAC Update Register or a timer trigger is received in one of the prescribed paths. Address: Type: Word Size: Bit Map: 15-0 AT-MIO-16X User Manual Base address + 10 (hex) Write-only 16-bit Name Description D<15..0> Data bus to the analog output DACs. The...
Page 141: Dac1 Register
DAC Update Register or a timer trigger is received in one of the prescribed paths. Address: Type: Word Size: Bit Map: 15-0 © National Instruments Corporation Base address + 12 (hex) Write-only 16-bit Name Description D<15..0> Data bus to the analog output DACs. The...
Page 142: Adc Event Strobe Register Group
The ADC Event Strobe Register Group consists of six registers that, when written to, cause the occurrence of certain events on the AT-MIO-16X board, such as clearing flags and starting A/D conversions. Bit descriptions of the six registers making up the ADC Event Strobe Register Group are given on the following pages.
Page 143: Configmemclr Register
CONFIGMEMCLR Register. Once the existing channel configuration values are cleared, they are not recoverable. At this point, the channel configuration memory is ready to be filled with valid information. © National Instruments Corporation Chapter 4 Base address + 1B (hex) Read-only...
Page 144: Configmemld Register
After strobing the DAQ Clear Register, the CONFIGMEMLD Register should be strobed to load the first value. A scanned data acquisition can be initiated from any location in the channel configuration memory by using this method. AT-MIO-16X User Manual Base address + 1B (hex) Write-only 8-bit...
Page 145: Daq Clear Register
If the channel configuration memory contains valid information and no new values are to be added before restarting the data acquisition sequence, the CONFIGMEMLD Register should be strobed following a DAQ Clear strobe. © National Instruments Corporation Chapter 4 Base address + 19 (hex) Read-only...
Page 146: Daq Start Register
DAQ Start Register Accessing the DAQ Start Register location initiates a multiple A/D conversion data acquisition operation. Note: Several other pieces of AT-MIO-16X circuitry must be set up before a data acquisition run can occur. See Chapter 5, Programming. Address: Type:...
Page 147: Single Conversion Register
EXTCONV* signal. The EXTCONV* signal is connected to the I/O connector, to OUT3 of the Am9513A, and to the A0 pin of the RTSI bus switch. If the Single Conversion Register is to initiate A/D conversions, all other sources of conversion should be inhibited to avoid an OVERRUN condition.
Page 148: Adc Calibration Register
Note: The ADC_BUSY* signal in Status Register 2 should be monitored to determine when the AT-MIO-16X ADC calibration cycle is finished. The calibration cycle takes approximately 1.25 sec to complete. All other conversions must be inhibited until the ADC calibration cycle is completed.
Page 149: Dac Event Strobe Register Group
The DAC Event Strobe Register Group consists of three registers that, when written to, cause the occurrence of certain events on the AT-MIO-16X board, such as clearing flags and updating the analog output DACs. Bit descriptions of the three registers making up the DAC Event Strobe Register Group are given on the following pages.
Page 150: Tmrreq Clear Register
A4RCV. If A4RCV is enabled, internal updating is selected and any signal from the RTSI switch can control the updating interval. If OUT2 is to be used for updating the DACs, A2DRV must also be enabled. If OUT5 is to be used, A4DRV must be enabled as well.
Page 151: Dac Update Register
DAC FIFO data for DAC0, DAC1, or both, as programmed. Address: Type: Word Size: Bit Map: Strobe Effect: © National Instruments Corporation Chapter 4 Base address + 18 (hex) Write-only 16-bit Not applicable, no bits used. Updates latched DAC values to the DAC Register in...
Page 152: Dac Clear Register
DAC FIFO. Address: Type: Word Size: Bit Map: Strobe Effect: AT-MIO-16X User Manual Base address + 1E (hex) Read-only 8-bit Not applicable, no bits used Empties the DAC FIFO, clears the TMRREQ bit in Status Register 1 and its associated interrupts, and...
Page 153: General Event Strobe Register Group
The General Event Strobe Register Group consists of six registers that, when written to, cause the occurrence of certain events on the AT-MIO-16X board, such as clearing flags and starting A/D conversions. Bit descriptions of the six registers making up the General Event Strobe Register Group are given on the following pages.
Page 154: Dma Channel Clear Register
The effect of the DMA channel Clear Register is to initialize this circuitry. Address: Type: Word Size: Bit Map: Strobe Effect: AT-MIO-16X User Manual Base address + 0B (hex) Read-only 8-bit Not applicable, no bits used Clears the dual DMA channel circuitry (dual DMA mode only) 4-58 ©...
Page 155: Dmatca Clear Register
Register is asserted. If DMATC interrupts are enabled, an interrupt will also be generated. Address: Type: Word Size: Bit Map: Strobe Effect: © National Instruments Corporation Chapter 4 Base address + 19 (hex) Write-only 8-bit Not applicable, no bits used Clears the DMATCA signal in Status Register 1, and...
Page 156: Dmatcb Clear Register
Address: Type: Word Size: Bit Map: Strobe Effect: AT-MIO-16X User Manual Base address + 09 (hex) Read-only 8-bit Not applicable, no bits used Clears the DMATCB signal in Status Register 1, and acknowledges an interrupt from a DMA Channel B...
Page 157: External Strobe Register
Address: Type: Word Size: Bit Map: Strobe Effect: © National Instruments Corporation Chapter 4 Base address + 1E (hex) Write-only 8-bit Not applicable, no bits used Generates an active-low pulse at the I/O connector of...
Page 158: Calibration Dac 0 Load Register
8-bit calibration DACs. Address: Type: Word Size: Bit Map: Strobe Effect: AT-MIO-16X User Manual Base address + 0A (hex) Write-only 8-bit Not applicable, no bits used Updates a selected calibration DAC 4-62...
Page 159: Calibration Dac 1 Load Register
12-bit ADC pregain offset calibration DACs. Address: Type: Word Size: Bit Map: Strobe Effect: © National Instruments Corporation Chapter 4 Base address + 1A (hex) Write-only 8-bit Not applicable, no bits used Updates the ADC pregain offset calibration DAC...
Page 160: Am9513A Counter/Timer Register Group
Am9513A Data Register. A detailed register description of all Am9513A registers is included in Appendix C, AMD Am9513A Data Sheet. Bit descriptions for the Am9513A Counter/Timer Register Group registers are given in the following pages. AT-MIO-16X User Manual 4-64 © National Instruments Corporation...
Page 161: Am9513A Data Register
Word Size: Bit Map: 15-0 © National Instruments Corporation Counter Mode Registers for Counters 1, 2, 3, 4, and 5 Counter Load Registers for Counters 1, 2, 3, 4, and 5 Counter Hold Registers for Counters 1, 2, 3, 4, and 5...
Page 162: Am9513A Command Register
Am9513A Counter/Timer and controls selection of the internal registers accessed through the Am9513A Data Register. Address: Type: Word Size: Bit Map: 15-8 AT-MIO-16X User Manual Base address + 16 (hex) Write-only 16-bit Name Description These bits must always be set when writing to the Am9513A Command Register.
Page 163: Am9513A Status Register
Counter 4 is at a logic high state. BYTEPTR This bit represents the state of the Am9513A Byte Pointer Flip-Flop. This bit has no significance for AT-MIO-16X operation because the Am9513A should always be used in 16-bit mode on the AT-MIO-16X. 4-67...
Page 164: Digital I/O Register Group
Digital I/O Register Group The two registers making up the Digital I/O Register Group monitor and control the AT-MIO-16X digital I/O lines. The Digital Input Register returns the digital state of the eight digital I/O lines. A pattern written to the Digital Output Register is driven onto the digital I/O lines when the digital output drivers are enabled (see the description for Command Register 2).
Page 165: Digital Input Register
Digital Input Register The Digital Input Register, when read, returns the logic state of the eight AT-MIO-16X digital I/O lines. Address: Type: Word Size: Bit Map: BDIO3 BDIO2 BDIO1 15-8 © National Instruments Corporation Base address + 1C (hex) Read-only...
Page 166: Digital Output Register
Register Map and Descriptions Digital Output Register Writing to the Digital Output Register controls the eight AT-MIO-16X digital I/O lines. The Digital Output Register controls both ports A and B. When either digital port is enabled, the pattern contained in the Digital Output Register is driven onto the lines of the digital port.
Page 167: Rtsi Switch Register Group
RTSI Switch Register Group The two registers making up the RTSI Switch Register Group, allow the AT-MIO-16X RTSI switch to be programmed for routing of signals on the RTSI bus trigger lines to and from several AT-MIO-16X signal lines. The RTSI switch is programmed by shifting a 56-bit routing pattern into the RTSI switch and then loading the internal RTSI Switch Control Register.
Page 168: Rtsi Switch Shift Register
Register Map and Descriptions RTSI Switch Shift Register The RTSI Switch Shift Register is written to in order to load the RTSI switch internal 56-bit Control Register with routing information for switching signals to and from the RTSI bus trigger lines. The RTSI Switch Shift Register is a 1-bit register and must be written to 56 times to shift the 56 bits into the internal register.
Page 169: Rtsi Switch Strobe Register
RTSI Switch Strobe Register The RTSI Switch Strobe Register is written to in order to load the contents of the RTSI Switch Shift Register into the RTSI Switch Control Register, thereby updating the RTSI switch routing pattern. The RTSI Switch Strobe Register is written to after shifting the 56-bit routing pattern into the RTSI Switch Shift Register.
Page 170: Register Programming Considerations
Note: If you plan to use a programming software package such as NI-DAQ or LabWindows/CVI with your AT-MIO-16X board, you need not read this chapter. Register Programming Considerations Several write-only registers on the AT-MIO-16X contain bits that control a number of independent pieces of the onboard circuitry.
Page 171: Initializing The At-Mio-16X
Chapter 5 Programming Counter Table 5-1 provides a general overview of the AT-MIO-16X resources to ensure there are no conflicts when using the counters/timers. As an example, if an interval scanning data acquisition sequence that requires less than 65,537 samples is in operation, Counters 2, 3, and 4 of the Am9513A are reserved for this purpose.
Page 172: Initializing The Am9513A
4. Disable all RTSI switch connections (see Programming the RTSI This sequence leaves the AT-MIO-16X circuitry in the following state: • • • • • • • Initializing the Am9513A Use the following sequence to initialize the Am9513A Counter/Timer. All writes are 16-bit operations. All values are given in hexadecimal.
Page 173: Figure 5-1. Initializing The Am9513A Counter/Timer
Chapter 5 Programming AT-MIO-16X User Manual START Write 0xFFFF to the Am9513A Command Register Write 0xFFEF to the Am9513A Command Register Write 0xFF17 to the Am9513A Command Register Write 0xF000 to the Am9513A Data Register ctr = 1 Write 0xFF00 + ctr to the...
Page 174: Programming The Analog Input Circuitry
Single Conversions Using the SCONVERT or EXTCONV* Signal Programming the analog input circuitry to obtain a single A/D conversion involves the following sequence of steps listed in Figure 5-2. © National Instruments Corporation Chapter 5 Programming AT-MIO-16X User Manual...
Page 175: Generating A Single Conversion
Single Conversion Register. To initiate a single A/D conversion through hardware, apply an active low pulse to the EXTCONV* pin on the AT-MIO-16X I/O connector. See the Timing Connections for Data Acquisition and Analog Output section in Chapter 2, Configuration and Installation, for EXTCONV* signal specifications.
Page 176: Reading A Single Conversion Result
The counters do not need reprogramming, and the next data acquisition operation starts when another trigger condition is received. © National Instruments Corporation and data was lost. obtain the result. Chapter 5...
Page 177 The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions section later in this chapter. AT-MIO-16X User Manual © National Instruments Corporation...
Page 178: Figure 5-3. Single-Channel Data Acquisition Programming
© National Instruments Corporation START Clear the A/D circuitry Program a single analog input channel, gain, mode, and range Program the sample-interval counter Program the sample counter Enable a single-channel data acquisition operation Apply a trigger Service the data acquisition operation Figure 5-3.
Page 179: Programming Data Acquisition Sequences With Channel Scanning
Programming Data Acquisition Sequences with Channel Scanning The preceding data acquisition programming sequence programs the AT-MIO-16X for multiple A/D conversions on a single input channel. The AT-MIO-16X can also be programmed for scanning multiple-analog input channels with different gain, mode, and range settings during the data acquisition operation.
Page 180: Figure 5-4. Scanning Data Acquisition Programming
Command Register 1 enables scanning during multiple A/D conversions. The SCANEN bit must be set regardless of the type of scanning used (continuous or interval); otherwise, only a single channel is scanned. © National Instruments Corporation START Clear the A/D circuitry...
Page 181: Interval-Channel Scanning Data Acquisition
The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions section later in this chapter. AT-MIO-16X User Manual 5-12 © National Instruments Corporation...
Page 182: Figure 5-5. Interval Scanning Data Acquisition Programming
© National Instruments Corporation START Clear the A/D circuitry Program multiple analog input channels, gains, modes, and ranges Program the sample-interval counter Program the sample counter Program the scan-interval counter Enable an interval scanning data acquisition operation Apply a trigger...
Page 183: Data Acquisition Programming Functions
A/D conversion results read from the FIFO are the results from the initiated conversions and are not left over results from previous conversions. AT-MIO-16X User Manual Analog input error flags OVERFLOW and OVERRUN are cleared Pending data acquisition interrupt requests are cleared...
Page 184: Programming Single-Analog Input Channel Configurations
If the SCANDIV bit is cleared, the channel configuration memory is incremented to the next entry after every conversion. The channel configuration memory must be loaded with the desired scan sequence before data acquisition begins. To load the channel © National Instruments Corporation 5-15 Chapter 5 Programming...
Page 185: Programming The Sample-Interval Counter
1. Write FF03 to the Am9513A Command Register to select the 2. Write the mode value to the Am9513A Data Register to store the AT-MIO-16X User Manual Strobe the CONFIGMEMCLR Register. For i = 0 to N-1, use the following steps:...
Page 186: Programming The Sample Counter(S)
Counter 5 available for general-purpose timing applications. If the desired sample count is greater than 65,536, both Counters 4 and 5 must be used. © National Instruments Corporation found in Appendix C, AMD Am9513A Data Sheet. Use one of the following mode values: 8225 —...
Page 187: Sample Counts 2 Through 65,536
4, and the upper 16 bits of the sample count are stored in Counter 5. All writes are 16-bit operations. All values given are hexadecimal. AT-MIO-16X User Manual Counter 4 Mode Register. mode value for posttrigger acquisition modes. Write 9025 to the Am9513A Data Register to store the Counter 4 mode value for pretrigger acquisition modes.
Page 188 A/D conversion pulses generated by Counter 3, and Counter 5 decrements every time Counter 4 reaches zero. The data © National Instruments Corporation Counter 4 Mode Register. mode value for posttrigger acquisition modes. Write 9025 to the Am9513A Data Register to store the Counter 4 mode value for pretrigger acquisition modes.
Page 189: Programming The Scan-Interval Counter
5. Write FF42 to the Am9513A Command Register to load Counter 2. 6. Write FFF2 to the Am9513A Command Register to step Counter 2 AT-MIO-16X User Manual Counter 2 Mode Register. Counter 2 mode value. Use one of the following mode values: 8225 —...
Page 190: Applying A Trigger
RTSI switch. To initiate the data acquisition operation through hardware, apply an active low pulse to the EXTTRIG* pin on the AT-MIO-16X I/O connector. See the Timing Connections for Data Acquisition and Analog Output section in Chapter 2, Configuration and Installation, for EXTTRIG* signal specifications.
Page 191: Servicing The Data Acquisition Operation
After a data acquisition operation terminates, if no errors occurred and the sample count was less than or equal to 10000 hex, the AT-MIO-16X is left in the same state as it was at the beginning of the data acquisition operation.
Page 192: Resetting A Single Am9513A Counter/Timer
(ctr - 1)}. If ctr is equal to 4, then 2 ^ (ctr - 1) results in 2 ^ 3, or 2 * 2 * 2, or 8. This result can also be obtained by shifting 1 left three times. © National Instruments Corporation 5-23 AT-MIO-16X User Manual...
Page 193: Figure 5-6. Resetting An Am9513A Counter/Timer
Am9513A Command Register Write 0xFF40 + 2 ^ (ctr -1) to the Am9513A Command Register AT-MIO-16X User Manual Disarm X mode Point to the Counter X mode register Store the Counter X mode value Point to the Counter X load register...
Page 194: Programming The Analog Output Circuitry
Programming the Analog Output Circuitry The voltages at the analog output circuitry output pins (pins DAC0 OUT and DAC1 OUT on the AT-MIO-16X I/O connector) are controlled by loading the DAC in the analog output channel with a 16-bit digital code. The DAC is loaded by writing the digital code to the DAC0 and DAC1 Registers, and then the converted output is available at the I/O connector.
Page 195: Cyclic Waveform Generation
Figure 5-7 must be followed. The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter. AT-MIO-16X User Manual 5-26 © National Instruments Corporation...
Page 196: Figure 5-7. Cyclic Waveform Programming
© National Instruments Corporation START Clear the analog output circuitry including the DAC FIFO Internal update ? Set the A4RCV bit in Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter...
Page 197: Programmed Cycle Waveform Generation
Figure 5-8. The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter. AT-MIO-16X User Manual 5-28 © National Instruments Corporation...
Page 198: Figure 5-8. Programmed Cycle Waveform Programming
© National Instruments Corporation START Clear the analog output circuitry including the DAC FIFO Internal update ? Set the A4RCV bit in Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter...
Page 199: Pulsed Cyclic Waveform Generation
The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter. AT-MIO-16X User Manual 5-30 © National Instruments Corporation...
Page 200: Figure 5-9. Pulsed Cyclic Waveform Programming
In this mode, Counter 1 counts the programmed number of cycles before terminating the sequence. Counter 2 then begins counting the time between cycles, the cycle interval, then restarts the sequence. This © National Instruments Corporation START Clear the analog output...
Page 201: Waveform Generation Programming Functions
Select a trigger line that is not being used. The signal must be routed from the selected B side trigger line to the A4 pin on the RTSI switch. All of this is done in one programming sequence by shifting a 56-bit value to the RTSI switch.
Page 202 After you complete this programming sequence, Counter n is configured to generate active-low pulses as soon as the load/arm counter command is written. © National Instruments Corporation Counter n Mode Register. Counter n mode value. Am9513A counter mode information can be found in Appendix C, AMD Am9513A Data Sheet.
Page 203: Programming The Waveform Cycle Counter
All writes are 16-bit operations. All values given are hexadecimal. 1. Write FF02 to the Am9513A Command Register to select the AT-MIO-16X User Manual Counter n Mode Register. mode value. Am9513A counter mode information can be found in Appendix C, AMD Am9513A Data Sheet.
Page 204: Servicing Update Requests
Register. If interrupts are enabled, an interrupt occurs when TMRREQ is set. In interrupt mode, TMRREQ must be cleared using the TMRREQ © National Instruments Corporation Counter 2 mode value. Am9513A counter mode information can be found in Appendix C, AMD Am9513A Data Sheet.
Page 205: Programming The Digital I/O Circuitry
Input Register. If the digital output ports are enabled, the Digital Input Register serves as a read-back register; that is, you can determine how the AT-MIO-16X is driving the digital I/O lines by reading the Digital Input Register. AT-MIO-16X User Manual 5-36 ©...
Page 206: Programming The Am9513A Counter/Timer
• • RTSI Bus Trigger Line Programming Considerations The RTSI switch connects signals on the AT-MIO-16X to the seven RTSI bus trigger lines. The RTSI switch has seven pins labeled A<6..0> connected to AT-MIO-16X signals and seven pins labeled B<6..0>...
Page 207: Rtsi Switch Signal Connection Considerations
AT-MIO-16X RTSI switch connections. RTSI Switch Signal Connection Considerations The AT-MIO-16X board has a total of nine signals connected to the seven A-side pins of the RTSI crossbar switch. These same signals also appear at the AT-MIO-16X I/O connector. As shown in Table 5-2, two AT-MIO-16X signals are connected to pin A2, and two signals are connected to pin A4.
Page 208: Programming The Rtsi Switch
OUT5. Programming the RTSI Switch The RTSI switch is a 7 7 crossbar switch which can be programmed to connect any of the signals on the A side to any of the signals on the B side and vice versa. To do this, a 56-bit pattern is shifted into the...
Page 209 Trigger Line 3. Conversely, if the B4 control field contains the pattern 1011, the signal connected to pin A5 appears at pin B4. This arrangement allows Trigger Line 4 to be driven by the AT-MIO-16X OUT1 signal. In this way, boards connected via the RTSI bus can send signals to each other over the RTSI bus trigger lines.
Page 210: Programming Dma Operations
Channel A and Channel B. The DMA channels are selected through Command Register 2. To program the DMA operation, perform the following steps after the circuitry on the AT-MIO-16X is set up: 1. Set the appropriate mode bits in Command Register 3 to enable 2.
Page 211 (DMA Channel B) are concurrently serviced, with buffer A serving DAC 0 and buffer B serving DAC 1. AT-MIO-16X User Manual AT-MIO-16X board. Refer to the IBM Personal Computer AT Technical Reference manual for more information on DMA controller programming.
Page 212: Interrupt Programming
Interrupt Programming Seven different interrupts are generated by the AT-MIO-16X board: • • • • • • • These interrupts can be enabled either individually or in any combination. In any of the interrupt modes, it is a good practice to confirm the source of the interrupt through reading Status Register 1.
Page 213: Calibration Procedures
Calibration Procedures This chapter discusses the calibration resources and procedures for the AT-MIO-16X analog input and analog output circuitry. The calibration process involves reading offset and gain errors from the analog input and analog output sections and writing values to the appropriate calibration DACs to null out the errors.
Page 214: Table 6-1. Eeprom Factory Area Information
User Reference 1 MSB User Reference 1 LSB The AT-MIO-16X is factory calibrated before shipment, and the associated calibration constants are stored in the factory area of the EEPROM. Table 6-1 lists what is stored in the EEPROM factory area.
Page 215 Location © National Instruments Corporation Table 6-1. EEPROM Factory Area Information (Continued) Location Description Reserved Board Code (AT-MIO-16X = 2) Revision and Sub-Revision Field Configuration Memory Depth ADC and DAC FIFO Depths Factory Reference Value MSB Factory Reference Value LSB...
Page 216 Chapter 6 Calibration Procedures Location When the AT-MIO-16X board is powered on, or the conditions under which it is operating change, the calibration DACs should be loaded with values from the EEPROM, or if desired, the board can be recalibrated. The AT-MIO-16X calibration process is not difficult or lengthy, and requires no external equipment (other than wires to connect the analog output to the analog input).
Page 217: Figure 6-2. Revision And Subrevision Field
0000 = A If the Revision and Subrevision Field contain the binary value 00100010, this signifies that the accessed AT-MIO-16X board is at Revision C and Subrevision 2. This number can be very useful in tracking boards in the field and in answering questions concerning board operation.
Page 218: Figure 6-4. Adc And Dac Fifo Depth Field
0000 = If the ADC and DAC FIFO Depth Field contains the binary value 00010011, then the AT-MIO-16X board that was accessed contains an ADC FIFO buffer of depth 512 and a DAC FIFO buffer of depth 2,048. This information is extremely useful in determining how many values to read from the ADC FIFO or write to the DAC FIFO when a half-full interrupt is generated.
Page 219: Calibration Equipment Requirements
Four times the accuracy of the AT-MIO-16X is ±0.000375% (±3.75 ppm). To redetermine the value of the reference on the AT-MIO-16X board you will need the following equipment: A precision DC voltage source (usually a calibrator):...
Page 220: Calibration Dacs
CALDAC6 CALDAC7 Reference Calibration The AT-MIO-16X has a stable voltage reference to which gain can be calibrated. The value of this voltage reference is determined through the reference calibration routine, which requires a known external voltage between 5 and 9.99 V to be connected differentially on any desired input channel.
Page 221: Analog Input Calibration
To eliminate this error source, the routine measures the internal voltage reference and adjusts CALDAC0 and © National Instruments Corporation Pregain offset (offset error at the input of the PGIA) Postgain offset (offset error at the input of the ADC)
Page 222: Analog Output Calibration
• • In order to read the analog output voltages, the output calibration routine requires that the AT-MIO-16X analog outputs be wrapped back to the analog inputs as follows: 1. Connect DAC0 to a channel in ACH<0..7> 2. Connect DAC1 to another channel in ACH<0..7>...
Page 223 DAC references. Hence, the gain of an analog output channel cannot be adjusted under software control if the channel is using an external reference (but the offset can still be adjusted). © National Instruments Corporation 6-11 AT-MIO-16X User Manual...
Page 224: Specifications
Specifications This appendix lists the specifications of the AT-MIO-16X. These are typical at 25° C unless otherwise stated. The operating temperature range is 0° to 70° C. A warmup time of at least 15 minutes is required. Analog Input Number of input channels ...16 single-ended, 8 differential Analog resolution ...16-bit, 1 in 65,536...
Page 225 System noise (including quantization noise) Crosstalk (other than from settling) ... –70 dB (DC to 100 kHz) Onboard reference ... 5.000 V (±2 mV) AT-MIO-16X User Manual After calibration ... ±3 V maximum Before calibration ... ±2.2 mV maximum Temperature coefficient... ±5 V/° C After calibration ...
Page 226: Table A-1. Equivalent Offset Errors In 16-Bit Systems
ADC systems and may be useful for comparing systems. They also apply to 16-bit DAC systems. 0 to 10 V –10 to 10 V © National Instruments Corporation Long-term stability...15 ppm Table A-1. Equivalent Offset Errors in 16-Bit Systems Range...
Page 227: Table A-2. Equivalent Gain Errors In 16-Bit Systems
Analog Data Acquisition Rates Single-Channel Acquisition Rates The maximum single-channel data acquisition rate of the AT-MIO-16X is 100 ksamples/sec (10- sec sample period). The AT-MIO-16X may run as fast as 111 ksamples/sec (9- sec sample period), but with unspecified accuracy.
Page 228: Table A-3. Typical Multiple-Channel Scanning Settling Times
Multiple-Channel Scanning Acquisition Rates When scanning among channels with different voltages, the analog circuitry on the AT-MIO-16X needs time to settle from one voltage to the next. Because of its complex transient response, the AT-MIO-16X is not always able to settle to full 16-bit accuracy within 10 sec, which is the shortest guaranteed sampling interval.
Page 229 Relative accuracy (nonlinearity)... ±4 LSB maximum, ±2 LSB Differential nonlinearity ... ±0.5 LSB maximum Offset error Gain error Onboard reference AT-MIO-16X User Manual After calibration ... ±305 V maximum Before calibration ... ±8.15 mV maximum Temperature coefficient... ±50 V/° C Using internal reference After calibration...
Page 230 The relative accuracy of the system is therefore limited to the worst-case deviation from the ideal correspondence (a straight line), excepting noise. If a DAC has been perfectly calibrated, then the relative accuracy specification reflects its worst-case absolute error. © National Instruments Corporation Appendix A ±10 V, bipolar mode, (software-selectable)
Page 231 Base clock available ... 5 MHz, 1 MHz, 100 kHz, Base clock accuracy ... ±0.01% Compatibility ... TTL-compatible inputs and Counter input frequency ... 6.9 MHz maximum (145-nsec AT-MIO-16X User Manual 2.4 V min 0.5 V max 1 frequency output...
Page 232 I/O connector ...50-pin male ribbon-cable Environment Operating component temperature ...0° to +70° C StorageTemperature ...–55° to +150° C Relative humidity ...5% to 90% noncondensing © National Instruments Corporation Appendix A connector or 68-pin male shielded cable connector Specifications AT-MIO-16X User Manual...
Page 233 I/O Connector This appendix describes the pinout and signal names for the AT-MIO-16X 50-pin I/O connector and the 68-pin I/O connector. Figure B-1 shows the AT-MIO-16X 50-pin I/O connector. © National Instruments Corporation Appendix AT-MIO-16X User Manual...
Page 234: Figure B-1. At-Mio-16X 50-Pin I/O Connector
AO GND ADIO0 ADIO1 ADIO2 ADIO3 DIG GND +5 V EXTSTROBE* EXTGA TE* SOURCE1 OUT1 GA TE2 SOURCE5 OUT5 Figure B-1. AT-MIO-16X 50-Pin I/O Connector AI GND ACH8 ACH9 ACH10 ACH11 ACH12 ACH13 ACH14 ACH15 DAC0 OUT EXTREF DIG GND BDIO0...
Page 235: Figure B-2. At-Mio-16X 68-Pin I/O Connector
Figure B-2 shows the pin assignments for the AT-MIO-16X 68-pin I/O connector. © National Instruments Corporation ACH0 ACH8 ACH1 AIGND AIGND ACH9 ACH2 ACH10 AIGND ACH3 ACH11 AIGND AISENSE ACH4 AIGND ACH12 ACH13 ACH5 ACH6 AIGND ACH14 AIGND ACH15 ACH7...
Page 236: Table B-1. Signal Connection Descriptions
39, 44, 50, 53 52, 17, 49, 47 25, 27, 29, 31 19, 51, 16, 48 26, 28, 30, 32 AT-MIO-16X User Manual Table B-1. Signal Connection Descriptions Signal Names AI GND Analog Input Ground—These pins are the reference point for single-ended measurements and the bias current return point for differential measurements.
Page 237 Table B-1. Signal Connection Descriptions (Continued) 68-Pin Pins 50-Pin Pins 8, 14 34, 35 © National Instruments Corporation Signal Names +5 V +5 VDC Source—These pins are fused for up to 1 A of +5 V supply. SCANCLK Scan Clock—This pin pulses once for each A/D conversion in the scanning modes.
Page 238 Appendix B I/O Connector Table B-1. Signal Connection Descriptions (Continued) 68-Pin Pins 50-Pin Pins AT-MIO-16X User Manual Signal Names OUT1 OUTPUT1—This pin is from the Am9513A Counter 1 signal. EXTTMRTRIG* External Timer Trigger—If selected, a high-to-low edge on EXTTMRTRIG* results in the output DACs being updated with the value written to them in the posted update mode.
Page 239 1. Copyright © Advanced Micro Devices, Inc. 1989. Reprinted with permission of copyright owner. All rights reserved. Advanced Micro Devices, Inc. 1990 Data Book Personal Computer Products: Processors, Coprocessors, Video, and Mass Storage. © National Instruments Corporation Appendix AT-MIO-16X User Manual...
Page 279: Electronic Services
Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24-hour support with a collection of files and documents to answer most common customer questions. From these sites, you can also download the latest instrument drivers, updates, and example programs. For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information, call (512) 795-6990.
Page 280: Telephone And Fax Support
Telephone and Fax Support National Instruments has branch offices all over the world. Use the list below to find the technical support number for your country. If there is no National Instruments office in your country, contact the source from which you purchased your software to obtain support.
Page 281 National Instruments for technical support helps our applications engineers answer your questions more efficiently. If you are using any National Instruments hardware or software products related to this problem, include the configuration forms from their user manuals. Include additional pages if necessary.
Page 282 Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Page 283 Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: AT-MIO-16X User Manual Edition Date: October 1997 Part Number: 320640B-01 Please comment on the completeness, clarity, and organization of the manual.
Page 284 Prefix Meanings pico- nano- µ- micro- milli- kilo- mega- giga- Numbers/Symbols percent positive of, or plus – negative of, or minus ° degree amperes alternating current © National Instruments Corporation Value Glossary AT-MIO-16X User Manual...
Page 286 Typically, a bus is the expansion vehicle to which I/O or other devices are connected. Examples of PC buses are the AT bus, NuBus, Micro Channel, and EISA bus. © National Instruments Corporation Glossary AT-MIO-16X User Manual...
Page 287: Calibration Dacs
(dB) code width the smallest detectable change in an input voltage of a DAQ device cold-junction a method of compensating for inaccuracies in thermocouple circuits compensation AT-MIO-16X User Manual © National Instruments Corporation...
Page 288 DAQ board to dissipate current for analog or digital output signals current sourcing the ability of a DAQ board to supply current for analog or digital output signals © National Instruments Corporation Glossary AT-MIO-16X User Manual...
Page 289 ADC resolution than is needed and (by means of feedback loops) pushes the quantization noise above the frequency range of interest. This out-of-band noise is typically removed by digital filters. AT-MIO-16X User Manual © National Instruments Corporation...
Page 290 LSB of the worst-case deviation of code widths from their ideal value of 1 LSB disk operating system down counter performing frequency division on an internal signal DRAM dynamic RAM © National Instruments Corporation Glossary AT-MIO-16X User Manual...
Page 291 (usually by ultraviolet light exposure) and reprogrammed equivalent-time sampling event the condition or state of an analog or digital signal expansion ROM an onboard EEPROM that may contain device-specific initialization and system boot functionality AT-MIO-16X User Manual © National Instruments Corporation...
Page 292 ADC whose output code is determined in a single step by a bank of comparators and encoding logic floating signal sources signal sources with voltage signals that are not connected to an absolute reference or system ground. Also called nonreferenced signal sources. © National Instruments Corporation Glossary AT-MIO-16X User Manual...
Page 294 The test signal is two sine waves added together according to the following standards: © National Instruments Corporation SMPTE—A 60 Hz sine wave and a 7 kHz G-11...
Page 295 CPU should suspend its current task to service a designated activity AT-MIO-16X User Manual sine wave added in a 4:1 amplitude ratio. DIN—A 250 Hz sine wave and an 8 kHz sine wave added in a 4:1 amplitude ratio.
Page 296 1,000 or 10 1,000 samples Kword 1,024 words of memory © National Instruments Corporation , used with B in quantifying data or bytes/s G-13 Glossary , used with units of...
Page 297 (1) Mega, the standard metric prefix for 1 million or 10 with units of measure such as volts and hertz; (2) mega, the prefix for 1,048,576, or 2 memory AT-MIO-16X User Manual , when used with B to quantify data or computer G-14 , when used...
Page 298 NuBus—a slot-dependent, 32-bit bus type used in Macintosh computers that has 32 interrupts and doesn’t use DMA normally closed, or not connected NI-DAQ NI driver software for DAQ hardware © National Instruments Corporation G-15 Glossary bytes/s AT-MIO-16X User Manual...
Page 299 Apple (the base OpenDoc architecture, the Bento file system and the Open Scripting Architecture) and IBM (the System Object Model) AT-MIO-16X User Manual G-16 © National Instruments Corporation...
Page 300 Intel to replace ISA and EISA. It is achieving widespread acceptance as a standard for PCs and work- stations; it offers a theoretical maximum transfer rate of 132 Mbytes/s. © National Instruments Corporation G-17 Glossary...
Page 302 Apple system software tools that make video presentation a standard part of the Macintosh. Applications can use QuickTime to record and display audio and video in the same way applications use system tools to generate and display text and graphics. © National Instruments Corporation G-19 Glossary AT-MIO-16X User Manual...
Page 303 Also called a grounded measurement system. resistance temperature detector—a metallic probe that measures temperature based upon its coefficient of resistivity AT-MIO-16X User Manual G-20 © National Instruments Corporation...
Page 304 RTSI Real-Time System Integration RTSI bus real-time system integration bus—the National Instruments timing bus that connects DAQ boards directly, by means of connectors on top of the boards, for precise synchronization of functions seconds samples sample counter the clock that counts the output of the channel clock, in other words, the number of samples taken.
Page 305 SPDT single-pole double throw—a property of a switch in which one terminal can be connected to one of two other terminals simultaneous sampling—a property of a system in which each input or...
Page 306 THD+N signal-to-THD plus noise—the ratio in decibels of the overall rms signal to the rms signal of harmonic distortion plus noise introduced © National Instruments Corporation G-23 Glossary AT-MIO-16X User Manual...
Page 307 For example, one pulse from the update clock produces one update which sends one new sample to every analog output channel in the group. AT-MIO-16X User Manual G-24 © National Instruments Corporation...
Page 308 VISA a new driver software architecture developed by National Instruments to unify instrumentation softwareGPIB, DAQ, and VXI. It has been accepted as a standard for VXI by the VXIplug&play Systems Alliance. visual basic custom...
Page 310 A/D conversion values (table), 4-33 two's complement mode A/D conversion values (table), 4-34 A/D converter, 3-6 © National Instruments Corporation ADC_BUSY* bit, 4-30 ADC Calibration Register, 4-52 ADC conversion timing, 3-8 ADC Event Strobe Register Group, 4-46 to 4-52...
Page 311 Am9513A Command Register, 4-66 Am9513A Data Register, 4-65 Am9513A Status Register, 4-67 programming general considerations, 5-37 AT-MIO-16X User Manual resource allocation considerations, 5-1 to 5-2 sample counters, 5-17 to 5-20 sample-interval counter, 5-16 to 5-17 scan interval counter, 5-20 to 5-21...
Page 312 A-3 to A-4 equivalent gain errors in 16-bit systems (table), A-4 equivalent offset errors in 16-bit systems (table), A-3 © National Instruments Corporation gain error, A-3 postgain offset error, A-3 pregain offset error, A-3 list of specifications, A-1 to A-2...
Page 313 A-6 to A-7 offset error, A-7 relative accuracy, A-7 AOGND signal analog output connections, 2-30 description (table), 2-17, B-4 AT-MIO-16X. See also specifications; theory of operation. block diagram, 3-1 features, 1-1 to 1-2 initializing, 5-2 to 5-3 National Instruments application...
Page 314 EEPROMCS, 4-5 EEPROMDATA, 4-29 EISA_DMA, 4-11 EXTREFDAC0, 4-11 EXTREFDAC1, 4-11 EXTTRIG_DIS, 4-24 FIFO/DAC, 4-24 GATE2SEL, 4-24, 5-32 © National Instruments Corporation INTCHB<2..0>, 4-19 INTGATE, 4-6 I/O_INT, 4-15 OUT<5..1>, 4-67 OUTEN, 5-40 OVERFLOW, 4-27, 5-7, 5-22 OVERRUN, 4-27, 5-7, 5-22 RETRIG_DIS, 4-6...
Page 315 5-43 programming digital I/O circuitry, 5-36 Command Register 3, 4-13 to 4-19 Command Register 4, 4-20 to 4-24 common-mode signal rejection, 2-29 AT-MIO-16X User Manual ComponentWorks software, 1-4 concatenating counters, 2-39 CONFIGCLK signal, 3-29 CONFIGMEM Register description, 4-35 to 4-40...
Page 316 2-37 pulse-width measurements, 2-38 time-lapse measurements, 2-38 timing requirements (figure), 2-41 timing specifications, 2-40 to 2-43 © National Instruments Corporation counter/timer. See Am9513A Counter/Timer Register Group; Am9513A System Timing Controller. customer communication, xvii, D-1 to D-2 cyclic waveform generation. See DAC waveform circuitry and timing;...
Page 317 3-20 to 3-22 DAC0 Register description, 4-44 programming analog output circuitry, 5-25 DAC0DSP bit, 4-21 DAC0OUT signal AT-MIO-16X User Manual analog output connections, 2-29 description (table), 2-17, B-4 programming analog output circuitry, 5-25 DAC0REQ bit, 4-18 to 4-19 DAC1 Register...
Page 318 5-16 to 5-17 scan-interval counter, 5-20 to 5-21 servicing data acquisition operations, 5-22 single conversions © National Instruments Corporation flow chart, 5-6 generating single conversions, 5-6 reading single conversion result, 5-7 using SCONVERT or EXTCONV* signal, 5-5 to 5-6...
Page 319 4-70 overview, 3-25 programming digital I/O circuitry, 5-36 register map, 4-2 Digital Output Register. See Digital I/O Register Group. AT-MIO-16X User Manual DIOPAEN bit description, 4-14 programming digital I/O circuitry, 5-36 DIOPBEN bit description, 4-13 programming digital I/O circuitry, 5-36...
Page 320 Register Group; DAC Event Strobe Register Group; General Event Strobe Register Group. event-counting application, 2-37 to 2-38 EXTCONV* signal © National Instruments Corporation description (table), 2-18, B-5 generating single conversions, 5-5 to 5-6 programming sample counter(s), 5-17 programming sample-interval counter, 5-16...
Page 321 GATE1 signal description (table), 2-18, B-5 RTSI switch connections (table), 5-38 GATE2 signal (table), 2-18, B-6 GATE2SEL bit AT-MIO-16X User Manual description, 4-24 pulsed cyclic waveform generation, 5-30 GATE5 signal (table), 2-18, B-6 General Event Strobe Register Group, 4-57 to 4-63...
Page 322 2-10 to 2-11 actual range and measurement precision (table), 2-11 selection considerations, 2-10 installation. See also configuration. hardware installation, 2-13 unpacking AT-MIO-16X, 1-7 INTCHB<2..0> bits, 4-19 internal update counter, selecting, 5-32 interrupts controlling with bits in Command Register 3, 4-13 to 4-19...
Page 323 (table), 2-22 single-ended connections (NRSE configuration), 2-28 offset error, analog output circuitry, A-7 operating environment specifications, A-9 operation of AT-MIO-16X. See theory of operation. optional equipment, 1-7 OUT, GATE, and SOURCE timing signals counter signal connections, 2-37 to 2-42...
Page 324 5-12 to 5-14 digital I/O circuitry, 5-36 to 5-37 initialization Am9513A, 5-3 to 5-4 AT-MIO-16X, 5-2 to 5-3 register programming considerations, 5-1 resource allocation considerations, 5-1 to 5-2 RTSI bus trigger line, 5-37 to 5-39 RTSI switch, 5-39 to 5-43...
Page 325 5-23 to 5-24 Am9513A Data Register, 4-65 Am9513A Status Register, 4-67 Analog Input Register Group, 4-31 to 4-40 AT-MIO-16X User Manual Analog Output Register Group, 4-41 to 4-43 analog output voltage versus digital code bipolar mode (table),...
Page 326 5-32 description, 4-59 interrupt programming, 5-43 programming DMA operations, 5-41 DMATCB Clear Register clearing analog output circuitry, 5-32 © National Instruments Corporation description, 4-60 interrupt programming, 5-43 programming DMA operations, 5-41 External Strobe Register, 4-61 General Event Strobe Register Group,...
Page 327 5-10 SCANCLK signal description (table), 2-18, B-5 multiple-channel data acquisition, 3-12, 3-13 timing connections, 2-33 timing I/O circuitry, 3-29 AT-MIO-16X User Manual SCANDIV bit description, 4-6 programming multiple-analog input channel configurations, 5-15 SCANEN bit continuous channel scanning data...
Page 328 5-15 single-channel data acquisition timing, 3-9 to 3-12. See also data acquisition programming. © National Instruments Corporation posttrigger data acquisition timing, 3-10 to 3-11 pretrigger data acquisition timing, 3-11 to 3-12 programming sequence, 5-7 to 5-9...
Page 329 3-15 to 3-18 block diagram, 3-16 calibration, 3-17 to 3-18 circuitry, 3-16 to 3-17 configuration, 3-17 AT-MIO-16X block diagram, 3-1 DAC waveform circuitry and timing, 3-18 to 3-24 FIFO continuous cyclic waveform generation, 3-22 to 3-23 FIFO programmed cyclic waveform...
Page 330 (table), 4-34 unipolar input, 2-10 unipolar mode, analog output voltage versus digital code (table), 4-42 unipolar output, 2-12 unpacking AT-MIO-16X, 1-7 update counter, selecting, 5-32 update-interval counter, programming, 5-32 to 5-33 VirtualBench software, 1-5 voltage reference calibration, 6-8 to 6-9 ©...

National Instruments DAQ AT-MIO-16X User Manual

Appendix A Specifications

Appendix B I/O Connector

Appendix Camd Am9513A Data Sheet

Appendix D Customer Communication

Chapter 1 Introduction

Chapter 2 Configuration and Installation

Chapter 3 Theory of Operation

Chapter 4 Register Map and Descriptions

Chapter 5 Programming

Chapter 6 Calibration Procedures

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Summary of Contents for National Instruments DAQ AT-MIO-16X