Gpctr0_Up_Down Signal; Gpctr1_Source Signal - National Instruments NI 6115/6120 User Manual

Multifunction i/o devices for pci/pxi/compactpci bus computers
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Chapter 4
Connecting Signals

GPCTR0_UP_DOWN Signal

This signal can be received as an input on the DIO6 pin and is not available
as an output on the I/O connector. The general-purpose counter 0 counts
down when this pin is at a logic low and count up when it is at a logic high.
You can disable this input so that software can control the up-down
functionality and leave the DIO6 pin free for general use.

GPCTR1_SOURCE Signal

Any PFI pin can receive as an input the GPCTR1_SOURCE signal, which
is available as an output on the PFI3/GPCTR1_SOURCE pin.
As an input, GPCTR1_SOURCE is configured in the edge-detection mode.
You can select any PFI pin as the source for GPCTR1_SOURCE and
configure the polarity selection for either rising or falling edge.
As an output, GPCTR1_SOURCE monitors the actual clock connected to
general-purpose counter 1, even if another PFI is externally generating the
source clock. This output is set to high-impedance at startup.
Figure 4-33 shows the timing requirements for GPCTR1_SOURCE.
t
p
t
t
w
w
t
= 50 ns minimum
p
t
= 10 ns minimum
w
Figure 4-33. GPCTR1_SOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 10 ns high or low. There is no minimum frequency limitation.
The 20 MHz or 100 kHz timebase normally generates GPCTR1_SOURCE
unless you select some external source.
© National Instruments Corporation
4-35
NI 6115/6120 User Manual

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