Figure 2-16. Slot-Select Timing Diagram - National Instruments SCXI-1121 User Manual

SLOT0SEL*
T
SS*X
Chassis Y
SS*11
Chassis 9
SERCLK
SERDATIN
T
ss _ dis
T
clk _ wait
T
slot0sel* _ wait
T
ss _ en
© National Instruments Corporation
ss_dis
T
clk_wait
SLOT0SEL* low to SS* disabled
SLOT0SEL* low to first rising edge on SERCLK
Last rising edge on SERCLK to SLOT0SEL* high
SLOT0SEL* high to SS* enabled
To write the 16-bit slot-select number to Slot 0, follow these steps:
1. Initial conditions:
SERDATIN = don't care
DAQD*/A = don't care
SLOT0SEL* = 1
SERCLK = 1
2. Clear SLOT0SEL* to 0. This will deassert all SS* lines to all modules
in all chassis.
3. For each bit, starting with the most significant bit, perform the
following action:
a. SERDATIN = bit to be sent. These bits are the data that is being
written to the Slot-Select Register.
b. SERCLK = 0
c. SERCLK = 1. This rising edge clocks the data.
4. Set SLOT0SEL* to 1. This will assert the SS* line of the module
whose slot number was written to Slot 0. If multiple chassis are being
used, only the appropriate slot in the chassis whose address
corresponds to the written chassis number will be selected. When no
communication is taking place between the data acquisition board and
any modules, it is recommended that 0 be written to the Slot-Select
Register to ensure that no accidental writes occur.
Chapter 2
0 1 0 0 1
Chassis ID = 9

Figure 2-16. Slot-Select Timing Diagram

2-43
Configuration and Installation
T
ss_en
T
slot0sel*_wait
1 0 1 1
Slot 11
200 nsec maximum
75 nsec minimum
250 nsec minimum
350 nsec maximum
SCXI-1121 User Manual