Figure 2-13. Slot-Select Timing Diagram - National Instruments SCXI-1120 User Manual

Chapter 2
SLOT0SEL*
T
ss_dis
SS*X
Chassis Y
SS*11
T
clk_wait
Chassis 9
SERCLK
SERDATIN
T
ss _ dis
T
clk _ wait
T
slot0sel* _ wait
T
ss _ en
To write the 16-bit slot-select number to Slot 0, follow these steps:
1. Initial conditions:
SERDATIN = don't care.
DAQD*/A = don't care.
SLOT0SEL* = 1.
SERCLK = 1.
2. Clear SLOT0SEL* to 0. This will deassert all SS* lines to all modules in all chassis.
3. For each bit, starting with the MSB, perform the following action:
a. SERDATIN = bit to be sent. These bits are the data that are being written to the
Slot-Select Register.
b. SERCLK = 0.
c. SERCLK = 1. This rising edge clocks the data.
4. Set SLOT0SEL* to 1. This will assert the SS* line of the module whose slot number was
written to Slot 0. If multiple chassis are being used, only the appropriate slot in the chassis
whose address corresponds to the written chassis number will be selected. When no
communication is taking place between the data acquisition board and any modules, you
should write zero to the Slot-Select Register to ensure that no accidental writes occur.
Figure 2-14 shows the timing requirements on the SERCLK and SERDATIN signals. You must
observe these timing requirements for all communications. T
SCXI-1120.
© National Instruments Corporation
SLOT0SEL* low to SS* disabled
SLOT0SEL* low to first rising edge on SERCLK
Last rising edge on SERCLK to SLOT0SEL* high
SLOT0SEL* high to SS* enabled

Figure 2-13. Slot-Select Timing Diagram

2-29
Configuration and Installation
0 1 0 0 1 1 0
Chassis ID = 9 Slot 11
is a specification of the
delay
T
ss_en
T
slot0sel*_wait
1 1
200 nsec maximum
75 nsec minimum
250 nsec minimum
350 nsec maximum
SCXI-1120 User Manual