I/O Extension Board - Yamaha DRX-2 Service Manual

DRX-2
There are two control lines which can overrule this reset
signal:
• IRESET_DIG (controlled by the microprocessor on the
Analogue Board).
• EJTAG_RESETn (only for production).
They can pull the output of the NCP303LSN29 (item 7106)
down via a shottky diode.
So when the output signal PNX7100_RESETn is 'low', the
board will reset. When this signal is 'high', the board is up
and running.
The PNX7100_SYS_RESETn is a general enabling signal
for the different reset lines. All other reset lines are directly
d r i v e n f r o m C h r y s a l i s
MPIO13_IDE1_RESETn). All and (item 7107) AND-gates.
If both reset signals are low, all other external devices are
initialized.
5.9 I2C Bus
The PNX7100 is the master of the I2C bus (during reset,
external I2C masters are allowed). The following ICs are
controlled by the I2C bus:
• IC7809.
• IC7810 NVRAMs.
• IC7004 VIP.
• IC7700 FLI2301 Video De-interlacer Line Doubler (for
Chrysalis-F boards).
• IC7703 ADV7196 Video Enc (for progressive scan
done by Chrysalis).
5.10 I/O Connectors
AIO Connector (item 1900)
The Audio In/Out (AIO) connector is used to interchange
digital audio signals between Analog- and Digital Board.
DAIO Connector (item 1901)
The Digital Audio In/Out (DAIO) connector is used to
interchange digital audio (SPDIF) signals between the
IOE-Board and the Digital Board.
VIO Connector (item 1904)
The Video In/Out (VIO) connector is used to interchange
analogue video signals between Analog- and Digital-
Board.
114
p o r t p i n s ( e . g .
5.11 Progressive Scan
Introduction
There are two versions foreseen, to generate a
progressive scan analogue video output:
• In the standard Chrysalis board, the 'low end'
progressive video output is generated by the PNX7100.
• In the Chrysalis 'F', the 'high end' progressive output is
generated by the Faroudja FLI2301. This IC offers
additionally DCDi, upscaling to HDTV, and picture
enhancement.
Description
The progressive scan part is integrated in the Digital
Board and built around the FLI2301 de-interlace/line
doubler (7701). This I2C controlled de-interlace uses a
64Mbit SDRAM (32bit x 2M) to perform high quality de-
interlacing (meshing). The de-interlace gets its digital YUV
input data from the PNX7100 (7400). The format of the
digital YUV input to the Fli2301 is CCIR656 with separated
Hsync, Vsync, and odd/even signal running on 27MHz.

6. I/O Extension Board

This board feeds the internal S/PDIF signal from the
Digital board to an optical and/or digital out connector. For
European players, also an YUV output is present on this
board.