Figure 3-27. Cpld Block Diagram - Motorola APX 3000 Detailed Service Manual

Theory of Operation
: Controller
3.2.4.8.8 CPLD (U6101)
The CoolRunner IC is a complex programmable logic device (CPLD) programmed specifically for the
APX product line. The CoolRunner IC is flash based and comes pre-programmed. It is contained in
an 8x8mm, 132 BGA package with 0.5mm ball spacing. The primary functions of the CPLD are clock
generation, GPIO expansion, SSI clock and frame sync direction control, F2 multiplexing, secure
data control, main display off-loading, and clock inversion.
An external linear regulator, U6508, supplies the CPLD's 1.875 V core voltage. The 1.875 V core
voltage is used for the CPLD's internal logic and I/O buffers. MAKO's 24.576 MHz clock source is
used by the CPLD to generate a 32.768 kHz clock for OMAP booting, real time clock/timer, and for
GPS. It is also used to generate 4.096 MHz for the MACE IC.
The CPLD is controlled through OMAP's EMIFS interface. It supports 31 configurable GPIOs. It also
supports 20 input only pins that are accessible through an EMIFS read operation. Some of the
GPIOs supported by the CPLD include GCAI_GPIO_0, F2_PARAMP_MON, and USB_CURR_LIM.
Some examples of the inputs the CPLD is programmed to support are some of the top and side
controls buttons (MON, SIDE_1 and SIDE_2) and board ID.
Figure 3-27 below shows the basic CPLD interfaces.
OMAP 1710
Processor
MAKO
F2 Select
F2 Timer
KEYLD_MISSING
GCAI GPIO0

Figure 3-27. CPLD Block Diagram

24MHz
CPLD
EMIFS
KL_SWITCH
3-35
4.096MHz to MACE
32kHz to GPS
32kHz to OMAP
GPIOs
GPIs