Figure 8-117.Memory Interface - Motorola APX 3000 Detailed Service Manual

Schematics, Boards Overlays, and Parts Lists: Main Board Block: UHF2 (84012616001)
DDR INTERFACE
U6302M6
OMAP1710
SDCLKX
SDCLK_EN
SBANK_0
SBANK_1
D6
0
SDATA_0 CONTROL NSRAS
C6
1
SDATA_1 NSCAS
C5
2
SDATA_2 CS_SDRAM
D7
3
SDATA_3 NSDQMU
D5
4
SDATA_4 NSDQML
C7
5
SDATA_5 DSQ_H
C4
6
SDATA_6
D8
7
SDATA_7 SADD_0
C10
8
SDATA_8 DATA SADD_1
D14
9
SDATA_9 SADD_2
D11
10
SDATA_10 SADD_3
C13
11
SDATA_11 SADD_4
C11
12
SDATA_12 SADD_5
D13
13
SDATA_13 SADD_6
D12
14
SDATA_14 ADDRESS SADD_7
C12
15
SDATA_15 SADD_8
SADD_9
SADD_10
SADD_11
SADD_12
SADD_13
DDR_DATA<17..0>
MMC INTERFACE
F2_TIMER_OUT
U6302M6
MMC1_CLK
OMAP1710
MMC1_CLKIN
MMC1_CMD
MMC1_CMDDIR
MMC1_DATDIR0
OPTION CARD INTF MMC1_DATDIR1
MMC1_DATDIR2
MMC1_DATDIR3
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
MMC2_CLK
MMC2_CMD
MMC2_CMDDIR
MMC2_DATDIR0
MEMORY CARD INTF
MMC2_DATDIR1
MMC2_DAT0
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3
R6301M6
10K
TP6307M6
TEST_POINT
DNP
TP6308M6
TEST_POINT
MT46H16M16LF
DNP
DDR_CLKX_1
D9
DDR_CLK_1 G2
C9
SDCLK
DDR_CLKE G3
H12
DDR_WE G1
H8 0
NSWE
DDR_BANK0
B3 1
DDR_BANK1 DDR_WE G7
C3 2 0
DDR_RAS DDR_CAS G8
H7 3 4
DDR_CAS DDR_RAS G9
B4 4 3
DDR_CS DDR_CRTL<6..0> DDR_CS H7
G8 5 5
DDR_UDM
D10
C8 DDR_LDM DDR_BANK0 H8
1
C14 DDR_DQSH H9
2
D4 DDR_DQSL J8
0
DSQ_L
A2 J9
0 1
B2 DDR_ADDR<2> K7
1 2
B6 DDR_ADDR<3> K8
2 3
A1 DDR_ADDR<4> K2
3 4
G10 DDR_ADDR<5> K3
4 5
B9 DDR_ADDR<6> J1
5 6
G12 DDR_ADDR<7> J2
6 7
G11 DDR_ADDR<8> J3
7 8
G9 DDR_ADDR<9> H1
8 9
B12 DDR_ADDR<10> J7
9 10
B8 DDR_ADDR<11> H2
10 11
H10 DDR_ADDR<12> H3
11 12
H9 DDR_UDM F2
12
H11 DDR_LDM F8
13
DDR_ADDR<13..0>
13
V11
M15
P11
P19
TP6301M6
P20 1
TEST_POINT
P18 DNP AVR_STATUS_1.8V
OUT
M14
R18
R11
V10
W10
W11
Y10
Y8
V9
V5
W19
W8
V8
W15
R10
CHANGES: REMOVE RSW_A, RSW_B, RSW_INT
REMOVE R6305, R6307, R63050
U6301M6
V_EXT_1.85
1
TP6304M6
TEST_POINT
TP6303M6 DNP
DNP
1
TEST_POINT
E2 DDR_DQSH
CLK
UDQS
E8 DDR_DQSL
CLK* LDQS
EN_CLKE
A8 DDR_DATA<0>
0
DQ0
B7 DDR_DATA<1>
1
WE
DQ1
B8 DDR_DATA<2>
2
CAS
DQ2
C7 DDR_DATA<3>
3
RAS
DQ3
C8 DDR_DATA<4>
4
EN_CS
DQ4
D7 DDR_DATA<5>
5
DQ5
D8 DDR_DATA<6>
6
BA0
DQ6
E7 DDR_DATA<7>
7
BA1
DQ7
E3 DDR_DATA<8>
8
A0
DQ8
D2 DDR_DATA<9>
9
A1
DQ9
D3 DDR_DATA<10>
10
A2
DQ10
C2 DDR_DATA<11>
11
A3
DQ11
C3 DDR_DATA<12>
12
A4
DQ12
B2 DDR_DATA<13>
13
A5
DQ13
B3 DDR_DATA<14>
14
A6
DQ14
A2 DDR_DATA<15>
15
A7
DQ15
A8
F3
A9
NC1 NC
PA_SHTDN
F7
A10_AP
NC2
A11
A12
R6492M6 FLASH INTERFACE
UDM
1.8K
LDM
TP6305M6
0 1
U6302M6
TEST_POINT
DNP
8 1
OMAP1710
TP6306M6
TEST_POINT
DNP
CONTROL
0 N4
FDATA_0
1 N2
FDATA_1
2 N7
FDATA_2
3 P2
FDATA_3
4 P4
FDATA_4
5 P7
FDATA_5
6 R2
FDATA_6
7 R3
FDATA_7
8 R4
FDATA_8 DATA
9 T2
FDATA_9
10 T3
FDATA_10
11 P8
FDATA_11
12 U1
FDATA_12
13 U3
FDATA_13
14 T4
FDATA_14 ADDRESS
15 V3
FDATA_15
V_EXT_1.85
V_EXT_1.85
PA_SHTDN
R6316M6
10K
FLASH_CTRL<8..0>
R6304M6
0
FLASH_RDY
7
V_EXT_1.85
R6306M6
10K
6 R6310M6
R6314M6 33
33 0
1 33 E6
R6311M6
CLK
L4 B4
CE
NF_ADV
M7 2 FLASH_OE_A F8
OE
NFCS_0
M3 8 4 33 G8
R6313M6 WE
NFCS_1
M4 TP6302M6 1 TEST_POINT 3 D4
RST
NFCS_2
N8 DNP 1 C6
WP
NFCS_3
U4 R6312M6 33 2 0 F6
ADV
NFOE
W1 3
NFRP
W2 4
NFWE
V4 1 A1
A1
NFWP
N3 6 2 B1
A2
FCLK
V2 7 3 C1
A3
FRDY
J8 1 4 D1
A4
FADD_1
D3 2 5 D2
A5
FADD_2
C1 3 6 A2
A6
FADD_3
E4 4 7 C2
A7
FADD_4
D2 5 8 A3
A8
FADD_5
F4 6 9 B3
A9
FADD_6
E3 7 10 C3
A10
FADD_7
J7 8 11 D3
A11
FADD_8
F3 9 12 C4
A12
FADD_9
G4 10 13 A5
A13
FADD_10
G3 11 14 B5
A14
FADD_11
G2 12 15 C5
A15
FADD_12
K8 13 16 D7
A16
FADD_13
H4 14 17 D8
A17
FADD_14
H3 15 18 A7
A18
FADD_15
K7 16 19 B7
A19
FADD_16
J2 17 20 C7
A20
FADD_17
J4 18 21 C8
A21
FADD_18
J3 19 22 A8
A22
FADD_19
F2 20 23 G1
A23
FADD_20
L8 21 24 H8
A24
FADD_21
K4 22 25 B6
A25_512M
FADD_22
K3 23 B8
A26_1G
FADD_23
NC
L7 24
FADD_24
E1 25
FADD_25
FLASH_ADDR<25..1>
FLASH_DATA<15..0>
CHANGES MADE
ADDED PA_SHTDN TO PORT M7 & R6492
8-193
V_FLASH
U6304M6
F7
WAIT
F2 0
DQ0
E2 1
DQ1
G3 2
DQ2
E4 3
DQ3
E5 4
DQ4
G5 5
DQ5
G6 6
DQ6
H7 7
DQ7
E1 8
DQ8
E3 9
DQ9
F3 10
DQ10
F4 11
DQ11
F5 12
DQ12
H5 13
DQ13
G7 14
DQ14
E7 15
DQ15
E8
RFU1 NC
F1
RFU2 NC
G2
RFU3 NC
H1
RFU4 NC
Figure 8-117. Memory Interface