Figure 8-55. Memory Interface - Motorola APX 3000 Detailed Service Manual

8-84
DDR INTERFACE
U6302
OMAP1710
SDCLKX
SDCLK
SDCLK_EN
NSWE
SBANK_0
SBANK_1
D6
0
SDATA_0 CONTROL NSRAS
1 C6
SDATA_1 NSCAS
2 C5
SDATA_2 CS_SDRAM
3 D7
SDATA_3 NSDQMU
4 D5
SDATA_4 NSDQML
5 C7
SDATA_5 DSQ_H
6 C4
SDATA_6 DSQ_L
7 D8
SDATA_7 SADD_0
8 C10
SDATA_8 DATA SADD_1
9 D14
SDATA_9 SADD_2
10 D11
SDATA_10 SADD_3
11 C13
SDATA_11 SADD_4
12 C11
SDATA_12 SADD_5
13 D13
SDATA_13 SADD_6
14 D12
SDATA_14 ADDRESS SADD_7
15 C12
SDATA_15 SADD_8
SADD_9
SADD_10
SADD_11
SADD_12
SADD_13
DDR_DATA<17..0>
MMC INTERFACE
F2_TIMER_OUT
U6302
MMC1_CLK
OMAP1710
MMC1_CLKIN
MMC1_CMD
MMC1_CMDDIR
MMC1_DATDIR0
OPTION CARD INTF MMC1_DATDIR1
MMC1_DATDIR2
MMC1_DATDIR3
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
MMC2_CLK
MMC2_CMD
MMC2_CMDDIR
MMC2_DATDIR0
MEMORY CARD INTF
MMC2_DATDIR1
MMC2_DAT0
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3

Figure 8-55. Memory Interface

V_EXT_1.85
R6301
TP6307
10K
TEST_POINT
DNP
TP6308
TEST_POINT
DNP
U6301
MT46H16M16LF
D9 DDR_CLKX_1
C9 DDR_CLK_1 G2
CLK
H12 DDR_CLKE G3
CLK*
H8 DDR_WE 0 G1
EN_CLKE
B3 DDR_BANK0 1
C3 DDR_BANK1 2 0 DDR_WE G7
WE
DDR_RAS DDR_CAS G8
H7 3 4 CAS
B4 DDR_CAS 4 3 DDR_RAS G9
RAS
G8 DDR_CS 5 DDR_CRTL<6..0> 5 DDR_CS H7
EN_CS
D10 DDR_UDM
DDR_LDM DDR_BANK0 H8
C8 1 BA0
C14 DDR_DQSH 2 H9
BA1
D4 DDR_DQSL 0 J8
A0
A2 0 1 J9
A1
DDR_ADDR<2>
B2 1 2 K7 A2
B6 2 3 DDR_ADDR<3> K8
A3
A1 3 4 DDR_ADDR<4> K2
A4
G10 4 5 DDR_ADDR<5> K3
A5
B9 5 6 DDR_ADDR<6> J1 A6
G12 6 7 DDR_ADDR<7> J2
A7
G11 7 8 DDR_ADDR<8> J3
A8
G9 8 9 DDR_ADDR<9> H1
A9
B12 9 10 DDR_ADDR<10> J7
A10_AP
B8 10 11 DDR_ADDR<11> H2
A11
H10 11 12 DDR_ADDR<12> H3
A12
H9 12 DDR_UDM F2
UDM
H11 13 DDR_LDM F8
LDM
DDR_ADDR<13..0> 13
V11
M15
P11
P19
TEST_POINT
P20 1
TP6301 DNP
P18 AVR_STATUS_1.8V
OUT
M14
R18
R11
V10
W10
W11
Y10
Y8
V9
V5
W19
W8
V8
W15
R10
CHANGES: REMOVE RSW_A, RSW_B, RSW_INT
REMOVE R6305, R6307, R63050
Schematics, Boards Overlays, and Parts Lists: Main Board Block: 700–800 MHz (84012501002)
1 TP6304 DNP
TEST_POINT
TP6303 DNP
1
TEST_POINT
E2 DDR_DQSH
UDQS
E8 DDR_DQSL
LDQS
A8 0 DDR_DATA<0>
DQ0
B7 1 DDR_DATA<1>
DQ1
B8 DDR_DATA<2>
2
DQ2
C7 3 DDR_DATA<3>
DQ3
C8 4 DDR_DATA<4>
DQ4
D7 5 DDR_DATA<5>
DQ5
D8 DDR_DATA<6>
6
DQ6
E7 7 DDR_DATA<7>
DQ7
E3 8 DDR_DATA<8>
DQ8
D2 9 DDR_DATA<9>
DQ9
DDR_DATA<10>
D3 10
DQ10
C2 11 DDR_DATA<11>
DQ11
C3 12 DDR_DATA<12>
DQ12
B2 13 DDR_DATA<13>
DQ13
B3 14 DDR_DATA<14> PA_SHTDN
DQ14
A2 15 DDR_DATA<15>
DQ15
FLASH_CTRL<8..0>
F3
PA_SHTDN
NC1 NC
F7
NC2
FLASH INTERFACE
R6492
1.8K
0 1 TP6305 DNP
R6314
TEST_POINT
33
U6302
8 1 TP6306 DNP OMAP1710
TEST_POINT
L4
NF_ADV
M7
NFCS_0
M3
NFCS_1
M4
NFCS_2
N8
NFCS_3
U4 R6312
NFOE
CONTROL
W1
NFRP
W2
NFWE
V4
NFWP
0 N4 N3
FDATA_0 FCLK
1 N2 V2
FDATA_1 FRDY
2 N7 J8
FDATA_2 FADD_1
3 P2 D3
FDATA_3 FADD_2
4 P4 C1
FDATA_4 FADD_3
5 P7 E4
FDATA_5 FADD_4
6 R2 D2
FDATA_6
FADD_5
7 R3 F4
FDATA_7 FADD_6
8 R4 E3
FDATA_8 DATA FADD_7
9 T2 J7
FDATA_9 FADD_8
10 T3 F3
FDATA_10 FADD_9
11 P8 G4
FDATA_11 FADD_10
12 U1 G3
FDATA_12 FADD_11
13 U3 G2
FDATA_13 FADD_12
14 T4 K8
FDATA_14 ADDRESS FADD_13
15 V3 H4
FDATA_15 FADD_14
H3
FADD_15
K7
FADD_16
J2
FADD_17
J4
FADD_18
J3
FADD_19
F2
FADD_20
L8
FADD_21
K4
FADD_22
K3
FADD_23
L7
FADD_24
E1
FADD_25
FLASH_DATA<15..0>
CHANGES MADE
ADDED PA_SHTDN TO PORT M7 & R6492
V_EXT_1.85
V_EXT_1.85
R6316
10K
R6304
0
7 FLASH_RDY V_FLASH
V_EXT_1.85
R6306
10K
U6304
0105955U25
6 R6310 33
0
1 R6311 33 E6
CLK
B4 F7
CE
WAIT
2 FLASH_OE_A F8
OE
G8 F2
8 4 R6313 33 WE
DQ0
1 TEST_POINT 3 D4 E2
RST
DQ1
DNP TP6302
1 C6 G3
WP
DQ2
33 2 0 F6 E4
ADV DQ3
E5
3
DQ4
4 G5
DQ5
1 A1 G6
A1
DQ6
6 2 B1 H7
A2 DQ7
C1
7 3 A3
1 4 D1 E1
A4
DQ8
2 5 D2 E3
A5
DQ9
3 6 A2 F3
A6 DQ10
C2 F4
4 7 A7
DQ11
5 8 A3 F5
A8
DQ12
6 9 B3 H5
A9
DQ13
7 10 C3 G7
A10 DQ14
E7
8 11 D3 A11
DQ15
9 12 C4
A12
10 13 A5
A13
11 14 B5 E8
A14
RFU1
F1
12 15 C5 A15
RFU2
13 16 D7 G2
A16
RFU3
14 17 D8 H1
A17
RFU4
15 18 A7
A18
16 19 B7 A19
17 20 C7
A20
18 21 C8
A21
19 22 A8
A22
20 23 G1 A23
21 24 H8
A24
22 25 B6
A25_512M
23 B8
A26_1G
NC
24
25
FLASH_ADDR<25..1>
C6308 C6309 C6310 C6311
0.1UF 0.1UF 0.1UF 0.1UF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NC
NC
NC
NC