Sharp MZ-5600 Service Manual page 23

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M Z-5600
Interrupt sequence
(1) If an interrupt request pulse is applied to one or more
of the interrupt request inputs (lA) of the 8259A, all
the pertinent bits of the interrupt request register
(I
A A) will be set.
(2) If the interrupt request is not masked, the 8259 sends
an INT signal to the CPU.
(3)
Upon receipt
ot
the INT signal, the CPU respons to it
with an acknowledge signal INTA.
(4)
When receiving the first
'JNTA,
the 8259 determines
the order of priority. When it is functioning as a
master, it outputs the number of the slave for which
the interrupt was acknowledged, to its CAS pin.
(5) When receiving the second
JNTA
from the CPU, the
8269 outputs an 8-bit
inte~rupt
vector address onto the
data bus synchronized with the second
INTA.
The CPU
reads this vector address at the trailing edge of the
INTA, and jumps to the interrupt routine specified by
the vector value.
IR~
INT _ _ _ _ .... '
\'----
'iNTA ------"'""'\
Data bus-------
-----------0--------
Vector
Fig. 19
4-7 Interrupt circuit
1. Block diagram
TG666
V-SYNC
IR-SIO
IR-PRT
IR-KEY
IR-NDP
IR-CTC
!lAO
lR-RTC
IR-FOC
IR-22
IR..,28
IR-24
IR-26
IR-26
!lA I
8086-2
NUl CPU
. - - - - - - - - I I N T R
,------___iADO-7
<D CID
- " " - - - _ _ _ i I RO I NT!-""::""--'
--~>-___i IRI
- - - - - I IR2 8269A
ill
- - - - - l I R a
j
11
nterrupt
- - - - - I I R 4 0 0 - 7 1 - - - - - +
vector
---<1"">---1
IR6
INT~---+-'
CA5
SOl2
5
5
8288
50
51
CID
52
t-----""--___i I NT A
--~.>_-1 IR2
-·<D---1
I
Ra
8269A
IR4
:>-----1
I R6 0 0 - 7 1 - - - -......
--~.>_-1
IR6 INT'A!E------'
- - - - - - i I R 7
(Slave)
2. Operational description
1) Non-maskable interrupt to the CPU will arise under one
of the following two (three) conditions.
a) Upon depression of the A ESET switch located on the
front side of the unit.
b) When trjed to access a memory and I/O area not
existing, but limited to the *XACK area on the map,
in order to chock an existence of a software bug or
-22-
connection of the optional board.
c) With the SEEG version of the MZ-5600, when a
certain task tried to access the memory area not per-
mitted to access.
(1)
When the software has run wild, the operation is::
normally halted by turning power off or resetting the ~
CPU. With this model the program is reset by the
soft~
ware using NMI in order to retain the AAM, except for
such a wild program run that may destroy the NMI
vector or NMI routine.
(2) Since this unit is the system of nonnally non-ready, the
ready signal is issued to the CPU or DMAC only when a
valid memory or I/O is .accessed. When an invalid
memory or
I/O is accessed, it makes
the system as if
halted. Therefore, if the ready signal has not returned
within a certain period, the ready signal is issued from
the timeout circuit which is sent to the CPU on the
NMlline.
Theory of ready signal generation from the timeout
circuit.
The one-shot multivibrator is triggered and its output ,
is kept high by the ALE signal which is issued at
the~
start of the bus cycle, when the CPU is continuing
effective access, or by the TG555 signal which
appears at the last stage of the DMA cycle or issued
normally at every 13 f.lS for memory refresh, when a
long internal processing such as multiplication is taken
place. But, the one-shot l;1lultivibrator output is in low
level when an invalid memory or I/O is accessed as it
does not contain the ALE or TG555 signal.
As the state of the AESET switch can be sensed
by~,j
means of the ASTSW signal which appears on the input
port (60H, bit 1), the reset NMI can be discriminated
from the timeout NMI.
(3) See the section discussing protection.
2) As all interrupts are controlled by the 8259A except for
NMI, request for interrupt is informed to the CPU after
evaluating their priority .
When there is an interrupt from a device by making the
I A input of the 8259A high, it causes the INTA of the·
CPU to go high, if the I A input is not masked. If
the~
CPU is ready for acception of interrupt, it makes the
interrupt acknowledge cycle executed so that the 8288
returns the INTA signal to the 8259A. Upon receiving
INTA, the 8259A sends on the data bus the vector
corresponding to that interrupt request. As there are two
I NT As, the interrupt request must be held until the first
INTA. If not, the 8259A assumes the action as if IA7 is
interrupted.
Timings
1) NMI
RESETSW
TG556
-.J'---'4-...J
NMI
_ _ _ ..J