Sharp MZ-5600 Service Manual page 20

I
I
t
Clock Input
CLK
", • • Input
Am
Cornrnend
.Mble
Input
CEN
I/O bul macIt _ " ' «tput
lOB
,U'l"
:t2"!.
j
PIn
functions
TIbIe'2
Pin
No.
19,3,18
2
S
16
4
6
15
1
12
11
13
8
9
7
14
17
Status decoda
Control signal
logic
Pin name Function
50,51,52 Status input
ClK
Clock input
ALE Address latch
enable output
DEN Data enable
DT/R Data transmit/
receive control
output
AEN Address enable
input
CEN
Command enable
input
lOB I/O bus mode
control input
AIOWC Advanced I/O
device write
control output
10WC I/O device write
control output
10RC
I/O device read
control output
AMWC Advanced memory
write control
output
MWTC Memory write
control output
MRDC Memory read
control output
INTA Interrupt
acknowledge
control output
MCE/PDEN
NU
Vcc
MROC
MW'fC
Command
~
genarator
Memory read control
Memory write control
Advanced mamory write control
-
M Z-5600
lORC
I/O davice read control
Command outputs
IOWC I/O device write control
AlOWC\
Advanced I/O device write control
mTA
Interrupt acknowledge control
DT/R Data send/receive control
Data enable
generator
DEN
/
- __ Master cascade enable/peripheral
)lCE PDEN
datll enable
ALE
Address latch eneble
GND
Fig. 16
IN/OUT
Description
IN Accept each status output SO - 52 from the CPU.
The 8288 produces command and control Signals from these input signals at
the appropriate timings. Each of these pins ha. a pull-up resistor.
IN Accepts the clock output (ClK) of the clock generator 8284.
The output timing of the 8288 varies with the clock rate applied to this pin.
OUT Provides a strobe to the address latch.
This pin is connected to the E pin of 74lS373 latch to latch address
information from the CPU.
OUT
Provides a data enable signal to the data bus transceivers on the local or
system bus (active high).
OUT Controls data flow between the CPU and memory or I/O devices.
When this pin i. high, the CPU is enabled to write data into a peripheral
device; when it is low, the CPU is enabled to read data from the device.
IN If this pin is set high with tha lOB input held at low, all the command
outputs are placed in three-.tate logic. If the lOB input is high,
this input causes the command outputs, other than
'i"5FiC,
10WC, AIOWC
and INTA, to be pieced in three-.tate logic.
IN If this pin is set low, all the command outputs, DEN and PO EN control
outputs are disabled (non-three-state logic).
If it is set high, these outputs are enabled.
IN If this pin is set high, the 8288 is placed in the I/O bus mode; if it is sat low.
the 8288 is placed in the system bus mode.
OUT Similar to the 10WC, this pin functions as an I/O device write control
output, but goes low one clock period in advance of the
lowe.
Active low output.
OUT
Active low output to command an 1/0 device to write the data onto
the data bus.
OUT Active low output to command an 1/0 device to read the data onto the
data bus.
OUT
Similar to the MWTC. this pin functions as a memory write control
output, bus goes low one clock period in advance to the MWTC.
Active low output.
OUT
Active low output to command memory to write the data from the
data bus.
OUT Active low output to command memory to output data onto the
data bus.
OUT
Indicates interrupt acknowledge to the device in request for interrupt
service, and commands the device to output the vector address onto
the data bus. Durirg an interrupt cycle, it functions the same way
as the 10RC, Active low output.
OUT
Master cascade enable or Peripheral data enable
-19-