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Pin functions
Pins having the same function in both Max. and Min.
modes.
Table 11-a
)
Pin No.
Pin name
Function
IN/OUT
Description
2-16
ADO-AD15
Address/data bus
IN/OUT
Used as address (AO:':'A 15) and data (00-015) buses by time-division
39
multiplexing.
35
A19/56
Address/status
OUT
Outputs the most significant 4 bits (A16-A19) of address information or
l
l
outputs
status information (53-56) by the time-division multiplexer. Address is output
38
A16/53
during T1 state, and status is output during T2, T3, TW, and T4 states. Bits 53
and 54 indicates which segment register is used for the current bus cycle.
54
53
0
0
Extra segment
0
1
5tack segment
1
0
Code segment or no segment used
1
1
Data segment
Bit 55 is an interrupt enable flag, and is updated at the beginning of each clock
cycle. Bit 56 is always zero.
34
BHE/57
Bus high enable/
OUT
Outputs bus high enable or status information by time-division multiplexing.
status output
Bus high enable is output during Tl state, while status information is output
during T2, T3, TW, and T4 states. The bus high enable, in conjunction with
AO, enables selection between byte·by-byte and word·by-word data handling.
BHE
AO
0
0
Word-by-word (16 bits)
0
1
High order byte
1
0
Low order byte
1
1
Not used.
32
RD
Read control
OUT
Active low output to indicate the timing of read operation from memory or
output
I/O ports.
22
READY
Ready input
IN
Indicates that the memory or peripheral device is ready for data communica·
tion. If this is low, the CPU completes the current read or write cycle after it is
set high.
18
INTR
Maskable inter-
IN
level sense terminal sampled at the last clock cycle of each instruction. This
rupt request input
input is maskable with the program, and is used, in conjunction with the
8259A, to request 256 type vector interrupts.
23
TE5T
Test input
IN
The CPU samples this input tly executing the WAIT instruction. If the Test
input is low, the CPU continues the current execution; if it is high, the CPU
repeats the idle cycle until the input is set low.
21
RE5ET
Reset input
IN
Used to initialize the internal logics of the CPU. This input must be maintained
at high for at least 4 clock cycles.
17
NMI
Non-maskable in-
IN
Non-maskable, edge trigger interrupt input sampled by the last clock of an
terrupt request
instruction execution cycle. Used for emergency interrupt such as power down,
input
and causes a type 2 interrupt.
-
..
19
ClK
Clock input
IN
Accepts an external clock source, usually the 8284A clock generator.
33
MX/MN
MAX/MINI
IN
Maximum/minimum mode select input
-16-
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