Sharp MZ-5600 Service Manual page 22

Block diagram
07
06
D5
Bidirectional
04
Data bus
dlta bus
D8
buffer
D2
01
DO
Write control input
RIId control Input
Addretllnput
AO
Chip .Iact input
CS
r' "
Cascade lines CAS 1
CAS 2
Slavl program input
m;;m
Enable buffer output
~.
Pin functions
Tabl.14
Pin No. Pin Name
Function
1
CS
Chip select input
2
WR Write control
input
3 RD Read control
input
4-11 07-00 Bidirectional
data bus
12.13.15
CAS2-CASO Cascade lines
16 SP/EN Slave program
control input/
enable signal
output
17 INT
I nterrupt request
output
18-25
IR7-IRO Interrupt request
inputs
26
iNTA
Interrupt
acknowledge
input
27 AO
Command/data
control input
8
Control logic
-
M Z-5600
TN'i'A
I nterrupt acknowledge inl?U.t
INT Interrupt request outp'!t
In-service
Priority
IRO
IRl
IR2
IRa
IR4
IR5
IR6
register
8
control
8
request
Interrupt request Inputs
8
(lSR)
logic
register
IN/OUT
IN
IN
IN
IN/OUT
IN/OUT
IN/OUT
OUT
IN
IN
IN
(lRR)
L-_~..I"-"C!J
IRT
InterNpt m .. k register (lMR)
(ID)
Fig. 18
Vcc (aY)
v ..
(OV)
Description
Active low input. but may be high during interrupt request input or
interrupt service sequence.
Controls command write from the data bus.
Controls data read onto the data bus.
All data and command transfers to or from the CPU is performed through
this bidirectional bus.
These lines are output when addressed as a master. and are input when
addressed as a slave. The master uses three-bit code to specify a slave via these
cascade lines. The slave compares the code on the cascade lines with its own
slave ID code. If agreement is found. it outputs data onto the data bus.
In normal mode. SP/EN = 1 specifies a master. and SP/EN = 0 specifies a
slave (SPI.
In the buffer mode. outputs a low level only if the data bus output
is enabled (EN).
Outputs an INT signal to the CPU when an interrupt request arriving at one
of the IR7 - IRO inputs is acknowledged.
Active high asynchronous interrupt request inputs (maskablel.
Order of priority can be altered.
Each input has a pull-up resistor.
For edge trigger operation. this input must be held high until the first INTA
is received.
Accepts an interrupt acknowledge from the CPU. When an INTA pulse is
received. the 8259 outputs a CALL command or vector address onto the
data bus.
Used in conjunction with the WA or AD signal to write commands or read
status information. Normally connected to one of the address lines.
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