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(4) Pin functions
Table 26
~--
- Pin No ..
Signal name
I/O
Description
1
CS
IN
Chip selector
2
CS
IN
Power down sense input
!
..
3
ADJ
IN
Used to adjust the seconds of
the real clock without using
r
the CPU.
r
4-7
AD-A3
IN
Address bus
I.
r
8
RD
IN
Read control output
9
GND
IN
OV pin
...
j
10
WO
OUT
Write control output
•
11-14
01-03
I/O
Data bus
15
ALARM
OUT
Provides a 1 Hz or 16Hz pulse
,
asan alrm
!
;
16-17
OSC I/O
I/O
Accepts a quarts-oscillator
18
Vcc
IN
+5V power supply
11.
PROGRAMMABLE SOUND
~
;
GENERATOR INTERFACE
11-1 Block diagram
AY-8-8I/12
RESET
A
I1
BDIR
B
SP
R/W
BCl
C
IDU
DAD
} FDD drive select & Motor
~:,
I
I
ID7
DA7
On signal
} Memory bank select
Fig~54
DAT-DAO
lffiFf
-
M Z-56 00
11-2 Logic Idescription
The programmable sound generator, AY-3-8912 has three
independent sound outputs to produce chords.
It contains a general-purpose 8-bit I/O port, and uses the
IOAO-IOA4 as the FDD drive selector and motor on
signals, and the IOA5-IOA7 as a bank selector for the
memory area AOOOOH through BFFFFH.
11-3 Programmable sound generator (PSG)
AY-3-8912
(1)
Highlights
1) Completely software-s;ontrolled sound generation.
2) Interfaces with almost all 8 or 16-bit microproces-
sors now available.
3) Three independent programmable analog outputs.
4) 8-bit general-purpose I/O port.
5) Single +5V power supply.
(2) Pin configuration
ANALOG CH C
TEST
2
Vcc 5V
3
ANALOG CH B
4
ANALOG CH A
5
GND
6
lOA 7
7
lOA 6
8
IOA5
lOA 4
10
IOA3
11
IOA2
12
lOA I
13
lOA 0
14
Fig. 55
(3) Block diagram
CLOCK
28
2:7
26
25
24
28
22
21
20
19
18
17
16
15
DAO
DAI
DA2
DA3
DA4
DA5
DA6
DA7
BCI
BC2
BDIR
A8
RESET
CLOCK
------t----
-----------
----,
REGISTER ARRAY
(16 READ/WR ITE
CONTROL REGISTERS)
RESET
RI!GI STERS
-47-
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