Sharp MZ-5600 Service Manual page 33

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M Z-5600
7·2 Operational description
As the 8237A programmable DMA controller is used, it has
four independent DMA channels. Channels a and 3 are
open for I/O slots; the channel a is dedicated for interface
with the hard disk, and the channel 3 is for interface with
the SFD.
Channel 1 is for interface with the standard MFD and is
provided with the DREQ delay circuit of 5 x 4 MHz clock
cycles in order to meet performance of DRQ through lORD
ofthe FDC.
Channel 2 is for refresh of the system RAM which 'is done
by reading the DRAM with the request from the CTC given
at every 13 IJ.S.
13PS
~~~
______
-=~
________
~~OOnl-
CTC
n
n
ZC/TOO
-----J
1'--_ _ _ _ _ _ _ _ _ _ ---1
L.. _ _ _
DREQ2~ I~\ ~
DACK2
Don't care Ur-------Do--n,"""t ... ;;=-r-,e
7·3 Timings
WhenDREQ appears on a channel, the DMAC issues the
hold request signal H RQ to the CPU. When the hold conver-
sion circuit receives this signal, it puts the CPU into the non
ready state to open the system bus. At the same time, the
hold acknowledge signal H LOA and DMA enable signal
cB
DMAE are returned to the DMAC to start DMA transfer . •
With the 8237 DMAC it is possible to control DMA transfer
of 16 bits in total (64 KB); Aa ,... A7 issued by the DMAC
itself and A8 ,... A 15 which DBO"" 7 are latched by ADSTB
at the start of the DMA transfer. To cover memory address
space of 1 MB of the 8086 CPU, 104-7 I/O (50H) latch
signals are used as A 16 .... A 19.
The DMAC goes
reMIY
with the DMA transferred memory
ready signal, and
one
WAIT is attached automatically to the
ready signal returned without a wait.
~
In the case of the DMA channel 1 (SW is not used for the channel 2)
CLK86
(8MHz)
CLK37
( 5MHz)
HRQ
HLDA
DACKI
READY
TG!i1i6
ADR
DATA
CMD
RDY
(82&1)
T40rTI
131max
CPU
address DMA address
DIIAD
.
DMA command
-
--------~
r-- - - - - - - -- - -
--of-----------.
*
The
CPU
clock
(CLK86)
is not in complete synchronization with the
DMA
clock
(CLK37).
...
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CPU
data
CPU command
~
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