Sharp MZ-5600 Service Manual page 21

-
M Z-5600
Status input versus command outputs
Table 13
S2 S1
L L
L L
L H
L
H
H L
H L
H H
H H
4·5 System clock
1. Block diagram
SO
L
H
L
H
L
H
L
H
14.7456 c:J
MHz
8086 status
Interrupt acknowledge
Data read from I/O port
Data write to I/O port
Hold
Instruction fetch
Data read from memory
Data write into memory
Passive state
8284A
X 1
OSCI--~
14.7456MHz
X2
24MHz
1 - - - - - - 1
EF 1
CLKt---~
8MHz/4.9152MHz
osc
+5V
~~--~~----~F/C
J,
DIP SW5
1...-_ _ ---'
106
CS( SOH)
2. Operational description
The MZ-5600 runs under two modes of CPU clocks; the
one under the high speed mode of 8 M Hz and the other
under the low speed mode of 4.9152 MHz, of which choice
is made by means of the system s\!"itch 5.
When SW5 = ON: 4.9152 MHz
When SW5
=
OFF: 8MHz
Since the state of the SW5 is represented by the bit 6 of the
input port (60H), it permits to identify the system clock.
Valid command output
INTA
10RC
10WC AIOWC
-
i-----'-
MRDC
~
'MW'rn" AMWc
-
4-8 8259A programmable interrupt controller
Highlights
(1) Single +5V power supply.
(2) Automatically produces a Interrupt vector to the CPU.
(3) Priority interrupt masks at each interrupt request
terminal and vector address specification are all pro-
grammable. ~
(4) Controls up to 64 levels of interrupt requests by
cascading the 8259.
(5) TTL compatible.
Pin configuration (top view)
Chip select input
CS_ Vcc
Write control input WR
-+
Read control input
Ri5 -+
07_
06_
05_
Bidirectional data bus
04_
03_
02_
DJ_
00-
~ CASO++
CUcade lines
CAS! ...
Vss_
Functional outline
Fig. 17
4-- AO Address input
+-
I NTA Interrupt acknowledge input
4 -
IR7
4 -
IR6
4 -
IR5
4 -
IR4
4-IRa
4-IR2
_IRI
_IRO
Interrupt request inputs
--+
INf
Interrupt request output
...... SP!EFl'
Sieve program input/enable buffer outpu
++ CAS2 Coocadolino
The 8259A is an integral interrupt controller with eight
levels of interrupt request input pins.
-20-
If an interrupt request arrives at one of the interrupt
request pins of the 8259A, it identifies the mask condition
and priority of the interrupt, then sends an INT signal to
the CPU. The 8259A subsequently delivers the prepro-
grammed vector address onto the data bus in response to
the INTA signal transferred from the system controller.