Sharp MZ-5600 Service Manual page 35

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M Z-5600
(4) Pin functions
Pin No.
Signal name
1
"R>R
2
IOW
3
MmJ!f
4 MEMW
S
(
-.
)
S READY
7 HLDA
8 ADSTB
9 AEN
10
HRO
11
CS
12 CLK
13
RESET
-
14
DACK 2
15 OACK3
24 DACK 1
25 DACKO
16 DRE03
17 DRE02
18 DREO 1
19 DREOO
20 GND
21-23
26-30
DB7-DBO
31 VCC
32-35 AO-A3
36
EOP
37-40 A4-A7
I/O Description
I/O
In Idle cycles, the CP U uses this signal as an input control to read the control register. In active cycles,
•
this signal is used as an output control signal with which the 8237A accesses data from peripheral
logics during OMA write operations.
I/O
In idle cycles, the CPU uses this signal as an input control to load information into the 8237A. In
active cycles, the 8237A uses it as an OYtput control to load data into peripheral logics during DMA
read operations.
OUT Used to access data from selected memory locations dUring DMA read.
(active low, three .. tate output).
OUT
Active low, three-state output used to write data into the selacted memory locetions during DMA
write.
IN This input must always be held high.
IN Used to extend the memory read/write pulse width (which is output by the 8237A) so as to accom-
modate low-speed memory or I/O devices.
//----
IN
Active high hold acknowledge signal sent from the CPU, indicating the CPU has relinquished system
bus access authority.
~
OUT
Active high address strobe used to strobe the high order address byte.
OUT
Used to enable the output of the latch holding the high-order 8 address bits, to output them onto the
system address bus. The AEN is also used to disable other system bus drivers during DMA transfer.
OUT
The 8237A uses this hold request Signal to request the CPU for the system bus access authority.
IN Chip selecting input.
,
IN Clock input.
,
IN
Asynchronous, active high input used to clear the command, status, request, and temporary registers.
:
l
OUT Indicates a DMA acknowledge to the peripheral logics.
IN
Independent, asynchronous channel request inputs used for peripheral logics to obtain DMA. DREO 0
has the highest priority and OR EO 3 the lowest.
j
OV pin.
Data bus output.
OUT
During DMA cycle, high-order 8 address bits are output onto the data bus, and are loaded into an
external latch by the ADSTB signal.
IN
+5V supply.
I/O
Low order 4 bits of the address bus. During idle cyles, these are input lines used for the 8237A to
address the control register to be read or loaded.
During active cycles, these are output lines used to furnish the low order 4 bits of address information.
I/O
Information pertaining to the end of DMA is available at this pin.
Low output
=
DMA end, or if forced LOW, forces DMA to end.
OUT High order 4 bits of address bus. These lines are enabled only during DMA.
1i
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