As-232C Interface - Sharp MZ-5600 Service Manual

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M Z-5600
(4) Pin functions
Table 27
Pin No.
Signal name
I/O
Description
1
ANALOG CH C
OUT
Analog output channel C
2
TEST1
Line test pin (must be unconnected).
3
Vcc
+5V power supply.
j
4
ANALOG CH B
OUT
5
ANALOG CH A
OUT
6
GND
7-14
IOA7-0
I/O
15
CLOCK
IN
16
RESET
IN
17
A8
IN
18
BDIR
IN
19
BC2
IN
20
BC1
IN
21-28
DA7-DAO
I~O
I
12-1 Logic description
ZBOACTC
llK)A SIO
RXUI
TXIE
ZCtr021--...--l
Control/data signals
Analog output channel B
Analog output channel A
OVpin
I/O port
Reference timing input for tone noise and envelope generators.
All internal registers are reset by applying a low level to this input at the time of power up.
Auxiliary address bit used to allocate not only the areas specified by DAC>-DA7, but .Iso extended
memory space.
Bus direction
These bus control signals control all the buses, internal or external, in the PSG.
Bus control 2
The PSG decodes these signals as follows:
Bus control 2
BDIR
BC2
BC1
PSC function
0
0
0
INACTIVE:
PSG/CPU bus is inactive, and DAC>-DA7
---
are set to a high impedance.
0
0
1
ADDRESS LATCH:
I ndicates the register address to be latched
into the PSG is on the bus.
0
1
0
INACTIVE:
0
1
1
READ
F~OM
PSG:
Transfers the contents of the currently
addressed register to the PSG/CPU bus.
1
0
0
ADDRESS LATCH:
1
0
1
INACTIVE:
1
1
0
WRITE TO PSG:
I ndicates the register data to be. latched into
the currently addressed register is on the bus.
1
1
1
ADDRESS LATCH:
When in Data mode: Corresponds to the register array bits BO-B7.
When in Address mode: DAC>-DA3 selects a register number, and DA4-DA7 is used for address input.
I
1
,
l
!
t
12. RS-232C INTERFACE
,
RI>
}Cbannel
so
(B)
Control.ignals
RI>
so
ST2
I~
KT
(A)
STI
m
Cl
clock for 100-9600 bauds to the SIO under software
f
c o n t r o l . '
To allow external synchronization for
~hannel
A,
the '
LS157 is switched by the PC2 output of the 8255, so that
I
the clock for the SIO may be furnished either from the
r
Z80CTC or an external source.
f
12-2 RS-232C interface specifications
Table 28
I/O format
RS-232C bit serial input/output
Channel
Two channels
J
l
:k
l
PB6..-_ _ _ _ _ ...J
Code
ASCII 7/8 bit code
f
~
Fig. 57
The RS·232C serial data interface has two channels, one of
which may be used for synchronous transmission. For
internal synchronization, the Z80CTC supplies a baud rate
-48-
Baud rate:
Synchronization
scheme:
Data format
LSI chip used:
110-9600 bps
i
CH. A (synchronous/start-stop or acynchro-
!
nors). CH: B (asynchronous start-stop)
I
Stop bit:
1/1.5/2
Parity:
Even/odd/none
,.
Z80 SIO and Z80A CTC
l
~
I

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