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the CPU differs from that viewed from the DMA
controller. Address switching occurs so that the re·
freshing specifications of 128 addresses/2ms is fulfilled.
RAM
DO-D7
L
2
o
RAM
D8-D15
H
8
1
CPUIddr.
(A1 - A18)
DO-D15
2
1
o
OMAaddr.
(AD- A16)
Fig.
28
5-3 Dynamic RAM read/write logic
• (1)
Block dieg,."
......
AI
L.S267
...
..
I
AI
All
=------'
Fig. 29
(2) Description
The CAS line uses a delay logic so that address is
output 40ns after the MRDC or AMWC signal is
output, and the
CAS
signal is output 70ns atter address
is output. The DACK2 signal applied to the input gate
of the delay logic is used to inhibit the CAS signal
during refreshing. The RAS signal is output when the
BR'Ai\.1.
*,
M R DC, and AMWC signals are all active. The
DACK2 is used to output the RAS signal during refresh
regardless of the chip select signals. (DRAM-.).
-25-
-
M Z-5600
(3) Dynamic RAM read/write timing
o 'SMHz Read cycle
T2
TB
TW
CLK86
ADR~~
_ _
~
______________
~L-~
____
~~
RA/CA
-------.....11
DRAM·ADR
DRAM DATA OUT
o 8MHz Write cycle
CLKIIII
~R-A~~~
__________________
-+ ______
~
__
86DATA OUT
1!A/CA _ _ _ _
.....I)
DRAM·ADR
5-4 Dynamic RAM refresh
(1)
Description of operation
Unlike the Z80, the 8086 has no refreshing logic. On
the MZ-5600 system, dynamic RAM refreshing is
accomplished by executing direct· memory access
(DMA) from memory to I/O at a certain interval.
(2) Timing chart
CutrT
ADR
---~~~.\
~
_ ______
~I·==~==l=ro~'~--------------------~
r;;ren-
\
r
IIAX202
iiiliC
RE
L
\~---'-
-------------------~~~~
~~
RA/CA
~
H
WE
H
(3) Description
Z80
CTC
Vcc
ZC/TOO
r--RF-R-Q~
Vcc
PR
D
Fig. 31
CL
Q
Fig. 32
8237
DACK2
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