Sharp MZ-5600 Service Manual page 19

4-3 8284 clock generator and driver
Highlights
(1)
Quartz-controlled oscillator with stable output fre-
quency.
(2) External clock input.
(3)
capable of producing a reset signal upon power on
when external resistors and capacitors are ullCl_
Pin configuration (top view)
Clock
oyne.
Input
CSYNC_
... rlpllor .. ·.loak output
PCLK _
Add_ ..
l1li. Input
III
'IIRl" _
RMCly
Input
III RDYI
-
'RMCIy output
READY_
RMCly
Input
121 RDYI
-
Acid ... _Ill.
Input
121
'DRT _
Cloak
output
CLK
-
(OV)
GND
Fig. 13
Block dlllram
_Vcc (IV)
-XI C/wIIII .... 'U
- XI
C/wIIII /llllul1IJ
_'JnItP ............. ......
".'1 ......... ......
_,~
CIIIII .... ......
... Ole . 0IIII .....
1UIIIUt .
~
'Ill'
,,-Input
_RBSET
"-toutput
Functional outline
The 8284 is a clock generator and driver designed exclusive-
ly for the 8086 processor. It contains a quartz-controlled
OICillator, frequency divider
(113)
to create the clock
output, frequency divider (112) to produce the peripheral
~
clock outpUt (peLK), reset logic
to
synchronize with the
~
eLK, aod ready logic. The
REI
Input accepts an external
.Ipl
that
I. used
to
produce a
CPU
reset
signal which is
synchronous with 'the eLK output, and uses a Schmitt
-trigger circuit In
Its
Input.
A power-on reset signal can be
procIaad by connecting a resistor and capacitor
to
this
mterml~
~-----------------------q«>----------------~D
F/e
EFl
Quartz-
controlled
OSC
4-4 8288 bus controller
Highlights
(1) Outputs with a large number of fan-outs.
CKO
D
FFl
(2) Advanced write control outputs (AIOWC and AMWC)
Pin configuration
1/0 bus mode t:ontrol input
lOB ......
C6V)
Ctock
input
eLK ......
Stlllu.input
ST ......
I
StICu'input
Frequency
divider 11/3)
SYNC
Fig. 14
Functional outline
CKO
Frequency
CKO divider (1/2)
FF2
0 ... IInd/receiYe control output DT
/R ....
17 ..... MCE/"P'fiEli
Miln,,~.
e"lbl. output/peripheral date
The 8288 is a bus controller and driver used with the 8086
CPU operating in the maximum mode. It decodes the SO-S2
outputs from the CPU into command and control signals
and provides control signals for I/O devices and memory.
The 8288 is usable in the multi-master configuration in
which more than one master CPU is attached to a single
data bus. The 8288 has an input pin to accept the control
signal AEN from the bus arbitor 8289.
Acktr •• "tch I"lble output
ALE ....
Add,.... l".bI. input
"'Am'.....
6
Memory rud control output lIROC'-
AdY.nc:ed memory write control output
AJIWC +-
Memory write control outp,lt ~ 4 -
(DV) GND
Fig. 15
D8t8 enlble output
Comn.nd e"_II.lnput
1/0 devic. rud control output
Adwnced I/O d",ice writ. control output
I/O deviel write control output
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