Sub Cpu (Main Unit: Ic303) - Icom ID-5100E Service Manual

• MAIN CPU (MAIN UNIT: IC300) (continued)
Ball
Line Name
No.
CI-V/CLONE UART data.
R4 CLOUT
(300–38400 bps)
DSP reset control.
R5 DSP_RESET
L=Reset.
Serial clock to the real time clock
R6 RTC_SCL
IC.
Main power supply line control.
R7 PCON
H= Power ON.
SD card write protect control.
R9 SD_PTC
H=Write protect.
R10 SCRES Sub CPU reset.
R11 SCTRG "TRG" signal to the sub CPU.
R12 SCTXS "TXS" signal to the sub CPU.
Common serial clock to the D/A
R13 CK
converter and expander.
External microphone connection
R14 MICSEL
detect.
AF output mute. (A band)
59 L_AFMUTE
H=Mute.
MIC mute switch control.
56 MICMUTE
H= Mute.
DSP clock shift control.
27 DCSFT
L=+600 Hz shifted.
17 R_PLLSTB PLL serial strobe. (Band B)
RX AF mute control. (Band B)
63 R_AFMUTE
L= Mute.
Modulation signal line switching
55 PLAY control.
H= Recorded audio is transmitted.
VHF band transmit circuit power
22 VTX_C control.
H= While transmitting.
UHF band transmit circuit power
23 UTX_C control.
H= While transmitting.
20 L_PLLSTB PLL serial strobe. (Band A)
Description I/O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
O
O
O
O

• SUB CPU (MAIN UNIT: IC303)

Ball
Line Name
No.
Reference
1 L_REFC
(Band A)
Reference
2 R_REFC
(Band B)
7 SCRES Sub CPU reset.
18 PLLCK PLL serial clock.
19 PLLDATA PLL serial data.
AF output control.
31 AF_SW H= AF signal is output from the ex-
AF mute control. (Band A)
24 L_RMUTE
L=Mute.
AF mute control. (Band B)
25 R_RMUTE
L=Mute.
Tone signal (CTCSS/DTCS) fi lter
26 DTCS_SEL switching control.
H=While sending DTCS signal.
Operating mode (FM/DV) switch-
ing control.
34 MAIN_DASEL
H= While operating in the DV
36 MIC1 Microphone gain control.
48 SCSCK Sub CPU clock.
49 SCTXD Sub CPU data to the main CPU.
50 SCRXD Main CPU data.
51 MIC2 Microphone gain control.
52 SCTRG "TRG" signal from the main CPU.
53 SCTXS "TXS" signal from the main CPU.
Demodulated
switching control.
57 VRX_RPT
H= While operating on the VHF
Demodulated
switching control.
58 URX_RPT
H= While operating on the UHF
Sub CPU clock frequency shift
60 CLSFT3 control.
H=Shifted.
61 CLSFT2*
Main CPU clock frequency shift
control.
62 CLSFT1*
Sub CPU "ACK" signal to the main
64 SCACK
CPU.
*: Clock frequency shifting range.
Line name CLSFT1
H
Line state H
L
4-8
Description
frequency control.
frequency control.
ternal speaker.
mode.
signal polarity
band.
signal polarity
band.
CLSFT2 Shifting range
H –1.2 kHz
L ±0 kHz
L +1.2 kHz
I/O
O
O
I
O
O
O
O
O
O
O
O
I
I
O
O
I
I
O
O
O
O
O