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2.Pin function
2/4
Pin No.
Symbol
30
HSYNC
31
VSS
32
VDD_3.3
33~35
NC
36
VDD_2.5
37
VSS
38~42
NC
43
PIO0
44
VSS
45
VDD_3.3
46~52
PIO1~7
53,54
MDATA0,1
55
VDD_3.3
56
VSS
57~62,63
MDATA2~7,15
64
VDD_3.3
65
VSS
66
MDATA14
67
VDD_2.5
68
VSS
69~73
MDATA13~9
74
VDD_3.3
75
VSS
76
MDATA8
77
LDQM
78
SD-CLK
79
CLKSEL
80,81
MADDR9,8
82
VDD_3.3
83
VSS
84~86
MADDR7~5
87
VDD_2.5
88
VSS
89
MADDR4
90
MWE
91
SD-CAS
92
VDD_3.3
93
VSS
94
SD-RAS
95
SD-CSO
96
SD-CS1
/MADDR11
97
SD-BS
98,99
MADDR10,0
100
VDD_3.3
101
VSS
102~104
MADDR1~3
105
RESERVED
106,107
NC
108
RESERVED
109
NC
110~112
RESERVED
113
DAI-LRCK
114
DAI-BCK
115
VDD_3.3
116
VSS
117
DAI-DATA
118,121
DA-DATA3~0
122
DA-LRCK
I/O
I/O
Horizontal sync.The decoder begins outputting pixel data for a new horizontal
line after the falling(active)edge of HSYNC.
Ground
Ground for core logic and I/O signals
Power
3.3-V supply voltage for I/O signals.
O
No connect
Power
2.5-V supply voltage for core logic
Ground
Ground for core logic and I/O signals
O
No connect
I/O
Programmable I/O pins.
Ground
Ground for core logic and I/O signals
Power
3.3-V supply voltage for I/O signals.
I/O
Programmable I/O pins.
I/O
SDRAM Data
Power
3.3-V supply voltage for I/O signals.
Ground
Ground for core logic and I/O signals
I/O
SDRAM Data
Power
3.3-V supply voltage for I/O signals.
Ground
Ground for core logic and I/O signals
I/O
SDRAM Data
Power
2.5-V supply voltage for core logic
Ground
Ground for core logic and I/O signals
I/O
SDRAM Data
Power
3.3-V supply voltage for I/O signals.
Ground
Ground for core logic and I/O signals
I/O
SDRAM Data
O
SDRAM Lower or Upper Mask
O
SDRAM Clock
I
Selects SYSCLK or VCLK as clock source.Normal operation is to tie HIGH.
O
SDRAM Address
Power
3.3-V supply voltage for I/O signals.
Ground
Ground for core logic and I/O signals
O
SDRAM Address
Power
2.5-V supply voltage for core logic
Ground
Ground for core logic and I/O signals
O
SDRAM Address
O
SDRAM Write Enable
O
Active LOW SDRAM Column Address
Power
3.3-V supply voltage for I/O signals.
Ground
Ground for core logic and I/O signals
O
Active LOW SDRAM Row Address
O
Active LOW SDRAM Chip Select 0
O
Active LOW SDRAM Chip Select 1 or use as MADDR11 for larger SDRAM
(64 Mbits).
O
SDRAM Bank Select
O
SDRAM Address
Power
3.3-V supply voltage for I/O signals.
Ground
Ground for core logic and I/O signals
O
SDRAM Address
I
Tie to VSS or VDD_3.3 as specified in Table 1.
O
No connect
I
Tie to VSS or VDD_3.3 as specified in Table 1.
O
No connect
I
Tie to VSS or VDD_3.3 as specified in Table 1.
I
PCM left/right clock.
I
PCM input bit clock.
Power
3.3-V supply voltage for I/O signals.
Ground
Ground for core logic and I/O signals
I
PCM data input.
O
PCM Data Out.Eight channels.Serial audio samples relative to DA_8CK and
DA_LRCK.
O
PCM Left Clock.ldentifies the channel for each sample.The polarity is program
mable
Function
UX-A10DVD
1-85
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