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3.Pin function
3/3
Symbol
I/O
Pin No.
91
SRDR
O
92
SFDR
O
93
SPRD
O
94
SPFD
O
95
FGIN
I
96
TEST1
I
97
TEST2
I
TEST3
I
98
99
DVSS
-
EFMO
O
100
CD4094BC (IC33) : Buffer
1.Pin layout
STROBE
1
16
DATA
2
15
CLOCK
3
14
Q1
4
13
Q2
5
12
Q3
6
11
Q4
7
10
V
8
9
SS
3.Block Diagram
STROBE
(2)
DATA
(3)
CLOCK
Sled servo drive PWM output. ( )
Sled servo drive PWM output. (+)
Spindle servo drive output. (PWM ( ) or polarity)
Spindle servo drive output. (PWM (+) or PWM absolute value)
Spindle CAV servo FG input.
Test pin. Connect to GND.
Test pin. Connect to GND.
Test pin. Connect to GND.
Digital ground.
Low when playback ; EFM (encoded data) output when recording.
2.Truth Table
Clock
V
DD
OUTPUT/ENABLE
Q5
Q6
Q7
Q8
Q'
S
Q
S
X=Don't Care
=HIGH-to-LOW
=LOW-to-HIGH
Note 1: At the positive clock edge,information in the 7th shift register stage is
transferred to Q8 and Qs
Q1
Q2
OUTPUT
(15)
(4)
(5)
ENABLE
Q1
Q2
D
D
D
CL
CL
(1)
D1
Q1
D2
Q2
D3
Q3
D4
CL
CL
CL
CL
CL
CL
CL
Function
Output
Strobe
Data
Enable
0
X
X
0
X
X
1
0
X
1
1
0
1
1
1
1
1
1
Q3
Q4
Q5
(6)
(7)
(14)
Q3
Q4
Q5
Q6
D
D
D
CL
CL
CL
CL
Q4
D5
Q5
D6
Q6
D7
Q7
CL
CL
CL
CL
CL
CL
CL
Parallel Outputs
Serial Outputs
Q1
Q
Q
s
N
(Note 1)
Hi-Z
Hi-Z
Q7
Hi-Z
Hi-Z
No Change
No Change
No Change
Q7
0
Q
-1
Q7
N
1
Q
-1
Q7
N
No Change
No Change
No Change
Q6
Q7
Q8
(13)
(12)
(11)
Q7
Q8
D
D
CL
CL
(9)
D8
Q8
Q
S
CL
CL
D
(10)
CL
Q'
Q
S
CL
UX-A10DVD
Q'
No Change
Q7
No Change
No Change
No Change
Q7
1-63
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