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UX-A10DVD
ZIVA-4.1-PBO (IC501) : AV decoder
1.Pin layout
A_VSS
SYSCLK
VCLK
A_VDD
DVD-DATA0/CD-DATA
DVD-DATA1/CD-LRCK
DVD-DATA2/CD-BCK
DVD-DATA3/CD-C2P0
DVD-DATA4/CDG-SDATA
VSS
VDD_3.3
DVD-DATA5/CDG-VFSY
DVD-DATA6/CDG-SOS1
DVD-DATA7/CDG-SCLK
VDACK
VREQUEST
VSTROBE
ERROR
VDD_3.3
RESERVED
VDD_3.3
VSS
NC
RESERVED
NC
HADDR0
HADDR1
HADDR2
RESERVED
RESERVED
RESERVED
VSS
VDD_2.5
RESERVED
VSS
VDD_3.3
RESERVED
RESERVED
RESERVED
RESERVED
HDATA7
VSS
HDATA6
HDATA5
HDATA4
HDATA3
HDATA2
VDD_3.3
VSS
HDATA1
HDATA0
CS
2.Pin function
1/4
Pin No.
Symbol
1
RD
2
R/W
3
VDD_3.3
4
WAIT
5
RESET
6
VSS
7
VDD_3.3
8
INT
9~12
NC
13
VDD_2.5
14
VSS
15~18
NC
19
VSS
20
VDD_3.3
21~28
VDATA0~7
29
VSYNC
1-84
157
208
I/O
I
Read strobe in I mode.Must be held HIGH in M mode.
I
Read/write strobe in M mode. Write strobe in I mode.Host asserts R/WLOW to
select Write and LOW to select Read for M mode only.
Power
3.3-V supply voltage for I/O signals.
O,OD,PU
Transfer not complete / data acknowledge.Active LOW to indicate host initiated
transfer is not complete.WAIT is asserted after the falling edge of CS and
reasserted when decoder is ready to complete transfer cycle.Open drain
signal,must be pulled-up via 1k
I
Active Low Reset.Assert for at least 5-milliseconds in the presence of clock to
reset the entire chip
Ground
Ground for core logic and I/O signals
Power
3.3-V supply voltage for I/O signals.
O,OD,PU
Host interrupt.Open drain signal,must be pulled-up via 4.7k
O
No connect
Power
2.5-V supply voltage for core logic
Ground
Ground for core logic and I/O signals
O
No connect
Ground
Ground for core logic and I/O signals
Power
3.3-V supply voltage for I/O signals.
O
Video data bus.Byteserial CbYCrY data synchronous with VCLK.At power-up,the
decoder does not drive VDATA.During boot-up,the decoder uses configuration
parameters to drive or 3-state VDATA.
I/O
Vertical sync.Bi-directional,the decoder outputs the top border of a new field on
the first HSYNC after the falling edge of VSYNC,VSYNC can accept vertical
synchronization or top/bottom field notification from an external source.
(VSYNC HIGH=bottom field.VSYNC LOW=Top field)
MADDR3
104
MADDR2
MADDR1
VSS
VDD_3.3
MADDR0
MADDR10
SD-BS
SD-CS1/MADDR11
SD-CS0
SD-RAS
VSS
VDD_3.3
SD-CAS
MWE
MADDR4
VSS
VDD_2.5
MADDR5
MADDR6
MADDR7
VSS
VDD_3.3
MADDR8
MADDR9
CLKSEL
SD-CLK
LDQM
MDATA8
VSS
VDD_3.3
MDATA9
MDATA10
MDATA11
MDATA12
MDATA13
VSS
VDD_2.5
MDATA14
VSS
VDD_3.3
MDATA15
MDATA7
MDATA6
MDATA5
MDATA4
MDATA3
MDATA2
VSS
VDD_3.3
53
MDATA1
MDATA0
Function
to 3.3 volts.Driven high for 10 ns before tristate.
to 3.3 volts.
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