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PREPARATION FOR USE
Table 2-23.
P1 Connector AC Characteristics
(Dual Port RAM Accessed Via System Bus)
Min.
Max.
Parameter (ns)
(ns)
Description
tAS
tDS
tOBD
tACK
tCMD
tAR
tDHW
tDHR
tXKH
tACC
tIR
tIPW
tCY
tRD
tDXL
tCS
tIS
50
-200
655
o
o
o
o
50
100
30
100
Address setup to command
Write data setup to command
877
on-board memory cycle delay
630
Command to XACK
Command width
Address hold time
Write data hold time
Read data hold time
57
Acknowledge hold time
488
Read to data valid
Inhibit hold time
Inhibit pulse width
915
Cycle time of board
500
Refresh delay time
Read data setup to XACK
Command separation
50
Inhibit setup time
NOTES: 1.
No refresh, dual port RAM not busy.
2.
Maximum
=
tRD
+
tOBD
+
tACK.
3.
Maximum access
=
tACC
+
tOBD
+
tRD.
4.
Maximum cycle
=
tCY
+
tOBD
+
tRD.
2-59
Remarks
From address to command
Note 1
No refresh
Notes 1 and 2
Note 1
Acknowledge turnoff
delay
Note 3
Note
4
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