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Summary of Contents for Intel IQ80219
- Page 1 ® Intel IQ80219 General Purpose PCI Processor Evaluation Platform Board Manual November 13, 2003 Document Number: 274022-001...
- Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
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Page 3: Table Of Contents
Interrupt Routing ... 37 ® Intel IQ80219 Evaluation Platform Board Peripheral Bus... 38 3.7.1 Flash ROM... 39 3.7.2 UART ... 40 3.7.3 HEX Display... 41 Board Manual Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Semihosting (File I/O) ... 23 Contents... - Page 4 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Contents 3.7.4 Rotary Switch... 42 3.7.5 Battery Status ... 43 Debug Interface ... 44 3.8.1 Console Serial Port... 44 3.8.2 Ethernet Port... 44 3.8.2.1 Intel 3.8.3 JTAG Debug ... 45 3.8.3.1 JTAG Port ... 45 3.8.4...
- Page 5 Displaying Source Code ... 97 B.7.4 Using Breakpoints... 98 B.7.5 Stepping Through the Code... 99 Board Manual Intel® IQ80219 General Purpose PCI Processor Evaluation Platform ® IQ80219 Memory Map ... 78 ® IQ80219 Physical Memory Map - Visual ... 79 ®...
- Page 6 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Contents B.7.6 Setting Code|Lab Debug Options ... 99 Exploring the Code|Lab Debug Windows ... 100 B.8.1 Toolbar Icons ... 100 B.8.2 Workspace Window ... 100 B.8.3 Source Code... 100 B.8.4 Debug and Console Windows ... 100 B.8.5...
- Page 7 Debugging Basics ...119 C.9.1 Overview ... 119 C.9.2 Hardware and Software Breakpoints ... 119 C.9.2.1 Software Breakpoints ... 119 C.9.2.2 Hardware Breakpoints ... 119 C.9.3 C.9.3 Exceptions/Trapping ... 120 Board Manual Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Contents...
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Page 8: Intel ® Iq80219 Evaluation Platform Board Peripheral Bus Topology......................................... 38
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Contents Figures ® Intel 80219 General Purpose PCI Processor Block Diagram ... 16 Serial-UART Communication ... 24 Ethernet-Network Communication... 24 JTAG Debug Communication ... 25 Functional Block Diagram... 31 Board Form Factor ... 32 External Interrupt Routing to Intel ®... - Page 9 46 Switch S7E1 - 8: Settings and Operation Mode ...59 47 Switch S8E1 - 2: Descriptions ... 60 48 Switch S8E1 - 2: Settings and Operation Mode ...60 49 Switch S8E1 - 3: Descriptions ... 60 Board Manual Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Contents...
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Page 10: Board Manual
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Contents 50 Switch S8E1 - 3: Settings and Operation Mode ... 60 51 Switch S8E1 - 4: Descriptions ... 60 52 Switch S8E1 - 4: Settings and Operation Mode ... 60 53 Switch S8E1 - 5: Settings and Operation Mode ... 61 54 Switch S8E1 - 5: Driver Mode Output Impedances ... -
Page 11: Revision History
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Contents Revision History Date Revision Description November 2003 Initial Release. Board Manual... - Page 12 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Contents This Page Left Intentionally Blank Board Manual...
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Page 13: Introduction
Intel evaluation platform for developers using 80219 as well as a Customer Reference Board (CRB). The IQ80219 is intended for general purpose, embedded application development. It is based on the 80219, a single-function device that integrates the Intel XScale compliant) with intelligent peripherals including a PCI bus application bridge. -
Page 14: Electronic Information
Table 2. Electronic Information Support Type The Intel World-Wide Web (WWW) Location: Customer Support (US and Canada): Component References Table 3 provides additional information on the major components of IQ80219. Table 3. Component Reference Component Part Number • Manufacturer: Intel Corporation Intel®... -
Page 15: Terms And Definitions
Customer Reference Board In-Circuit Emulator – A piece of hardware used to mimic all the functions of a microprocessor. Joint Test Action Group – A hardware port supplied on Intel XScale JTAG evaluation boards used for in-depth testing and debugging. -
Page 16: Intel ® 80219 General Purpose Pci Processor
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Introduction ® Intel 80219 General Purpose PCI Processor ® About the Intel 80219 general purpose PCI processor (80219). The 80219 combines the Intel XScale purpose, embedded applications. This single-function PCI device is fully compliant with the PCI Local Bus Specification, Revision 2.2. - Page 17 Bus Specification, Revision 1.0a. Also, the processor supports a 66 MHz conventional PCI mode as ® defined by the PCI Local Bus Specification, Revision 2.2. The addition of the Intel XScale core brings intelligence to the PCI bus application bridge.
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Page 18: Intel ® Iq80219 Evaluation Platform Board Features
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Introduction ® Intel IQ80219 Evaluation Platform Board Features Table 5. Summary of Features Feature Battery Backup Unit: Battery back up circuit for SDRAM – 64 MB for 72 hours. Ethernet Port: Gigabit Ethernet Debugging/Download Port (using Intel® 82544). -
Page 19: Getting Started
PCI/PCI-X slot. When using a backplane, an ATX rated power supply is required. The IQ80219 only draws from the 3.3 V line of the power supply. Most ATX power supply units (PSUs) regulate off the 5 V signal. When there is nothing drawing from the 5.5 V signal most ATX PSU do not supply the 3.3 V correctly. -
Page 20: Factory Settings
Development Strategy 2.4.1 Supported Tool Buckets For developing and debugging software application, the production version of the IQ80219 kit includes the Code|Lab Development Environment. Support for the Code|Lab development environment is available from ATI*. Please refer to the enclosed package. -
Page 21: Target Monitors
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Target Monitors 2.5.1 Redhat Redboot RedBoot* is an acronym for “Red Hat Embedded Debug and Bootstrap”, and is the standard embedded system debug/bootstrap environment from Red Hat, replacing the previous generation of debug firmware: CygMon and GDB stubs. -
Page 22: Arm Firmware Suite
— Timer support. — Interrupt Controller support. µHAL manages all the variables associated with the IQ80219. This is provided in source form for users to embed and distribute in their own products running on an 80219. Included also as sources and with object distribution rights are: —... -
Page 23: Arm Angel
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 2.5.2.1 ARM Angel Angel is one of the debug monitor programs for 80219. It is provided in source and binary form with the ARM Software Development Toolkit. It features: • Debug capability, including memory inspection, image download and execution, break-pointing and single step •... -
Page 24: Host Communications Examples
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started Host Communications Examples How to communicate to the host. 2.6.1 Serial-UART Communication Using a serial connection: Figure 2. Serial-UART Communication Host System SW Debugger Host System fi Intel 80219 General Purpose PCI Processor 2.6.2... -
Page 25: Jtag Debug Communication
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 2.6.3 JTAG Debug Communication Using a JTAG Emulator: Figure 4. JTAG Debug Communication Host System SW Debugger Host System fi Intel 80219 General Purpose PCI Processor Board Manual C/C++ Parallel Port Getting Started... -
Page 26: Gnupro Gdb/Insight
When the final state of “A1” does not occur, reset the processor again. The time for reset is approximately 1 or 2 seconds. Win32 on Host Connecting with HyperTerminal. ® IQ80219 evaluation platform board. While the 'reset' is asserted, the two Board Manual... - Page 27 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform To bring up a HyperTerminal session on a Win32 platform: Go to Start, Programs, Accessories, Communications, HyperTerminal • HyperTerminal setup screens: — “Connection Description” Panel: • Enter name. — “Connect To” Panel: •...
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Page 28: Connecting With Gdb
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started 2.6.4.2 Connecting with GDB Below are the GDB commands entered from the command prompt. Be sure system path is set to access “xscale-elf-gdb.exe”. File name in example “hello”. Bold type represents input by user: >xscale-elf-gdb -nw hello... -
Page 29: Arm Extended Debugger
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 2.6.5 ARM Extended Debugger For further information on the AXD Debugger, refer to the content of the ARM ADS. This setup assumes that Angel is Flashed on the board: Description: Terminal emulator runs on host and communicates with the board via the serial cable. - Page 30 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started This Page Left Intentionally Blank Board Manual...
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Page 31: Hardware Reference Section
Hardware Reference Section Functional Diagram Figure 5 shows the functional block for the IQ80219. Figure 5. Functional Block Diagram Memory Battery Backup PC1600 DDR Memory DDR Memory Bus fi Intel 82544 Giga Ethernet FET Quick Switches PCI-X Bridge Primary PCI-X Bus 64-bits, 133 MHz... -
Page 32: Board Form-Factor/Connectivity
82544 Gigabit Ethernet Controller for network connectivity. The IQ80219 can electrically isolate the Intel The IQ80219 has one serial port/UART (compatible with 16C550). The IQ80219 has one JTAG port compliant with ARM Multi-ICE 20-pin connector standard. The JTAG is targeted for the Intel ® XScale core and is used for software debug purposes. -
Page 33: Power
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Power The IQ80219 draws power from the PCI-X bus. The power requirements for the IQ80219 are shown Table 7 below. The numbers do not include the power required by a PCI-X card mounted on the expansion slot. -
Page 34: Memory Subsystem
The board features two banks of DDR SDRAM in the form of one two-bank dual inline memory module (DIMM), only Un-buffered PC1600 DIMMs. ® The Intel IQ80219 evaluation platform board has a single DIMM connector supporting the DIMM arrangements listed in Table 9. Supported DIMM Types Type... -
Page 35: Flash Memory Requirements
IQ80219 May be programmed using the PCI-X interface – Flash Recovery Utility (FRU) Utility. IQ80219 May be programmed using a RAM based software target monitor – Redhat Redboot and ARM Firmware Suite. IQ80219 May be programmed using a JTAG emulation/debug device. -
Page 36: Intel ® 80219 General Purpose Pci Processor Operation Mode
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section ® Intel 80219 General Purpose PCI Processor Operation Mode Please refer to user switches section for mode setting during reset. Board Manual... -
Page 37: Interrupt Routing
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Interrupt Routing The IQ80219 Interrupt routing. Figure 7. External Interrupt Routing to Intel ® Intel 80219 General Purpose PCI Processor Board Manual ® 80219 General Purpose PCI Processor XINT0 XINT1 XINT2 XINT3... -
Page 38: Intel ® Iq80219 Evaluation Platform Board Peripheral Bus
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section ® Intel IQ80219 Evaluation Platform Board Peripheral The IQ80219 populates the peripheral bus as depicted by ® Figure 8. Intel IQ80219 Evaluation Platform Board Peripheral Bus Topology FLASH 28F640J3A... -
Page 39: Flash Rom
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 3.7.1 Flash ROM Table 12. Flash ROM Features ® Flash is an Intel StrataFlash Flash size is 8 MB The connection to the peripheral bus is depicted by Figure 9. Flash Connection on Peripheral Bus ®... -
Page 40: Uart
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.7.2 UART Table 13. UART Features UART on the peripheral bus is part of the 16C550 family. The connection to the peripheral bus is depicted by Figure 10. UART Connection on the Peripheral Bus ®... -
Page 41: Hex Display
HEX Display on the Peripheral Bus ® The Intel IQ80219 evaluation platform board includes a HEX Display unit on the peripheral bus. The HEX display contains two digits (MSB, LSB). The connection to the peripheral bus is depicted by Figure 11. -
Page 42: Rotary Switch
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.7.4 Rotary Switch The IQ80219 provides a Rotary Switch for the user to select from different boot-up flavors. Table 15. Rotary Switch Requirements Rotary switch has a 4-bit resolution (16 positions). -
Page 43: Battery Status
Battery Status Buffer Requirements ® The Intel IQ80219 evaluation platform board provides the following status for the battery: • Battery-Present status-bit on PB data line 9 • Battery-Charge status-bit on PB data line 10 • Battery-Discharge status-bit on PB data line 12 The connection to the peripheral bus is depicted by Figure 13. -
Page 44: Debug Interface
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section Debug Interface 3.8.1 Console Serial Port The platform has one serial port for debug purposes as described in Evaluation Platform Board Peripheral Bus” on page 3.8.2 Ethernet Port The IQ80219 supports an Intel ®... -
Page 45: Jtag Debug
PCI-X BUS. The IQ80219 has Mictor connectors for Logic Analyzer connection on the Peripheral Bus. The IQ80219 can facilitate placing a DDR Logic Analyzer Interface card – Connects to the DDR DIMM connector in place of the DIMM. Board Manual... -
Page 46: Micor J3F2 Signal/Pins
PB_AD<0> PB_AD<1> PB_AD<2> PB_AD<3> PB_AD<4> PB_AD<5> PB_AD<6> PB_AD<7> PB_AD<8> PB_AD<9> PB_AD<10> PB_AD<11> PB_AD<12> ® IQ80219 evaluation platform board. When voltage is applied, particularly Mictor Pin Mictor Pin Name Name Schematic Signal Name PB_AD<13> PB_AD<14> PB_AD<15> PB_AD<16> PB_AD<17> PB_AD<18> PB_AD<19> PB_AD<20>... -
Page 47: Micor J2F1 Signal/Pins
Schematic Signal Name FWE* PB_RST* HOLDA HOLD READY* BLAST* DEN* FOE* PB_CLK ADS* F_A<0> F_A<1> F_A<2> F_A<3> Board Manual ® IQ80219 evaluation platform board. When voltage is applied, particularly Mictor Pin Mictor Pin Name Name Hardware Reference Section Schematic Signal Name... -
Page 48: Micor J1C1 Signal/Pins
S_AD<28> S_AD<27> S_AD<26> S_AD<25> S_AD<24> S_AD<23> S_AD<22> S_AD<21> S_AD<20> S_AD<19> S_AD<18> S_AD<17> S_AD<16> ® IQ80219 evaluation platform board. When voltage is applied, particularly Mictor Pin Mictor Pin Name Name Schematic Signal Name S_AD<15> S_AD<14> S_AD<13> S_AD<12> S_AD<11> S_AD<10> S_AD<9> S_AD<8>... -
Page 49: Micor J3C1 Signal/Pins
S_AD<57> S_AD<56> S_AD<55> S_AD<54> S_AD<53> S_AD<52> S_AD<51> S_AD<50> S_AD<49> S_AD<48> Board Manual ® IQ80219 evaluation platform board. When voltage is applied, particularly Mictor Pin Mictor Pin Name Name Hardware Reference Section Schematic Signal Name S_AD<47> S_AD<46> S_AD<45> S_AD<44> S_AD<43> S_AD<42>... -
Page 50: Micor J2C1 Signal/Pins
Schematic Signal Name S_FRAME* S_DEVSEL* S_TRDY* S_C/BE<2> S_C/BE<3> S_REQ* S_GNT* S_RST* INTD* INTC* INTB* INTA* ® IQ80219 evaluation platform board. When voltage is applied, particularly Mictor Pin Mictor Pin Name Name Schematic Signal Name S_ACK64* S_REQ64* S_CLK0 S_C/BE<4> S_C/BE<5> S_C/BE<6> S_C/BE<7> S_C/BE<0>... -
Page 51: Reset Requirements/Schemes
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Board Reset Scheme Figure 15 depicts the reset scheme for the IQ80219. Table 23. Reset Requirements/Schemes Primary PCI reset, resets all devices on the board. It occurs during the power-up. The SRST signal from the JTAG connector is a bi-directional signal that can force a reset similar to the power-up reset on the board. -
Page 52: Switches And Jumpers
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.10 Switches and Jumpers 3.10.1 Switch Summary Table 24. Switch Summary Switch Association S7E1-1 S7E1-2 S7E1-3 S7E1-4 SPCI-X Bus S7E1-5 SPCI-X Bus S7E1-6 SPCI-X Clock Set SPCI-X clock configuration... -
Page 53: Pcix Initialization Summary
• PCI-X 100/133 The IQ80219 platform is by default set to operate this bus in PCI-X 66 MHz mode. The loading on the secondary PCI-X bus may result in marginal operation when speed is greater than that. When an expansion card is placed on the PCI-X expansion slot, the mode is based on the least capable device on the bus. -
Page 54: Default Switch Settings - Visual
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.10.3 Default Switch Settings - Visual Table 25. Switch S7E1 S7E1 S7E1 Use opposite settings when using an 80300-BP Backplane from Cyclone Micro Systems or most other PCI-X backplanes (switches S7E1-3, S8E1-7, S4D1-1, 2, 3, 4). -
Page 55: Jumper Summary
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 3.10.4 Jumper Summary Table 31. Jumper Summary Jumper Association J1G2 PPCI-X Reset J3E1 SPCI-X Clock J3G1 PCI-X Bridge J9E1 PCI-X Bridge J9F1 PCI-X Bridge 3.10.5 Connector Summary Table 32. Connector Summary Connector... -
Page 56: Secondary Pci/Pci-X Operation Settings
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.10.7 Secondary PCI/PCI-X Operation Settings Table 34. Secondary PCI/PCI-X Operation Settings S7E1-6 S7E1-7 133 MHz operation is not planned. 100 MHz operation is marginal due to the number of PCI-X loads and has not been validated. The results may vary depending on what devices plug into the expansion slot. -
Page 57: Detail Descriptions Of Switches/Jumpers
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 3.10.9 Detail Descriptions of Switches/Jumpers 3.10.9.1 Switch S7E1- 2/3 Table 36. Switch S7E1- 2/3: General Descriptions Switch Association S7E1-2 S7E1-3 3.10.9.1.1 S7E1-2: RST_MODE RESET MODE is latched at the de-asserting edge of P_RST# and it determines when the 80219 is held in reset until the Intel XScale Table 37. -
Page 58: Switch S7E1- 4/5
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.10.9.2 Switch S7E1- 4/5 Table 40. Switch S7E1 - 4/5: Descriptions Switch Association S7E1-4 S7E1-5 3.10.9.2.1 Switch S7E1 - 4 This allows 80219 to hide the device in PCI-X Slot 1under GPIO control. -
Page 59: Switch S7E1- 8
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 3.10.9.4 Switch S7E1- 8 Table 45. Switch S7E1 - 8: Descriptions Switch Association S7E1-8 SPCI-X Clock Table 46. Switch S7E1 - 8: Settings and Operation Mode S7E1-8 Enable S_CLK<4..0>. Disable S_S_CLK<4..0>. Board Manual... -
Page 60: Switch S8E1- 2
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.10.9.5 Switch S8E1- 2 Turn On to enable on-board Gigabit Ethernet, otherwise Off for better PCI-X loading/performance. Table 47. Switch S8E1 - 2: Descriptions Switch Association S8E1-2 Table 48. -
Page 61: Switch S8E1- 5
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 3.10.9.8 Switch S8E1- 5 When this input is pulled high (off), the bridge changes the output impedance of the drivers to the opposite state than was assumed by default, as shown in 3.10.9.8.1... -
Page 62: Switch S8E1- 7
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.10.9.10 Switch S8E1- 7 Used to enable the IDSEL reroute function at reset or power-up. The reset value of the secondary bus private device mask register is modified according to the tie value of the IDSEL_REROUTE_EN pin. -
Page 63: Switch S8E2 - 1/2
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 3.10.9.12 Switch S8E2 - 1/2 This feature forces the PCI-X Capability pins for the expansion slot to force a configuration on the Secondary PCI-X bus. Table 62. Switch S8E2 - 1/2: Descriptions... -
Page 64: Switch S9E1 - 1:3
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.10.9.14 Switch S9E1 - 1:3 Table 66. Switch S9E1 - (1:3) Descriptions Switch Association S9E1-1:3 PCI-X Bridge Table 67. Switch S9E1 - (1:3) Settings and Operation Mode S9E1-1 3.10.9.15 Switch S9E1 - 4 Table 68. -
Page 65: Switch S1D1 - 1/2
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 3.10.9.16 Switch S1D1 - 1/2 Switches 1 and 2 have to always be opposite of each other. Table 70. Switch S1D1 - 1/2: Descriptions Switch Association S1D1-1 2 3 DDR Memory Table 71. -
Page 66: Jumper J1G2
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section 3.10.9.19 Jumper J1G2 Table 76. Jumper J1G2: Descriptions Jumper Association J1G2 PPCI-X Reset Table 77. Jumper J1G2: Settings and Operation Mode J1G2 Pins 1,2 P_RST (primary side reset) disconnected from reset circuitry. -
Page 67: Jumper J9E1
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 3.10.9.22 Jumper J9E1 Base Address Register Enable: Used to enable the base address register at reset or power-up. The 64-bit register located at offsets x'10' and x'14' is used to claim a 1 MB memory region when enabled. The register returns all zeroes to read accesses and the associated memory region is not claimed when disabled. - Page 68 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Hardware Reference Section This Page Left Intentionally Blank Board Manual...
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Page 69: External Raid Section
External RAID Section The IQ80219 provides the capability for the user to develop RAID applications. There is a requirement to provide the ability of making the secondary PCI-X devices private and the ability to route the interrupt lines. The following requirements describe this capability. -
Page 70: Interrupt Routing
Number The INTA# and INTB# of PCI-X Expansion Slot are routed to XINT0# and XINT1# External 4.2.1 Interrupt inputs on the 80219. The INTA# of Intel 82544 Controller is routed to XINT2# External Interrupt input on the 4.2.2 80219. 4.2.3 The interrupt routing scheme is based on Figure 18. -
Page 71: Software Reference
7 of 12. The appropriate Base address and Limit registers must be set for each of the six chip enables (PCE0-5). Each peripheral and its corresponding PCE# are described in this section. All registers associated with the PBI can be found in the Intel Processor Developer’s Manual, section 8.6, table 128. -
Page 72: Flash Rom
Intel 80219 General Purpose PCI Processor Under normal operation, the very first instruction access by the Intel XScale 0x0 on the 80219 Internal Bus. By default, address 0x0 is pointing to PCE0 where flash is located. ® See the Intel... -
Page 73: Uart
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 5.2.2 UART The UART is a TL16C550C. It sits on the Peripheral Bus and is accessed using PCE1 and XINT1# as shown in Figure Figure 20. UART Connection to Peripheral Bus ®... -
Page 74: Hex Display
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Software Reference 5.2.4 HEX Display The HEX Display is an Agilent* HDSP-G211, which allows for monitoring of two digits. It sits on the Peripheral Bus and is accessed using PCE2 and PCE3 as shown here: Figure 21. -
Page 75: Register Bitmap: 7-Segment Display Lsb Fe85 0000H (Write Only)
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Software Reference Figure 24. Register Bitmap: 7-Segment Display LSB FE85 0000h (Write Only) Board Manual... -
Page 76: Ethernet
ARM-AFS, Redboot, VxWorks* and other standard OSs come with support for this chip. For more detail see controller. For programming information please refer to the Intel® 82544EI/82544GC Gigabit Ethernet Controller Software Developer’s Manual. Section 3.8.2 of this manual for a detailed description of the onboard Ethernet... -
Page 77: Board Support Package (Bsp) Examples
IQ80321 board. ® 5.4.1 Intel 80219 General Purpose PCI Processor Memory Map Figure 25 depicts the memory space for the IQ80219 (before Redboot boots): ® Figure 25. Intel 80219 General Purpose PCI Processor Memory Map 0000 0000h - 7FFF FFFFh... -
Page 78: Redboot* Intel ® Iq80219 Memory Map
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Software Reference 5.4.2 Redboot* Intel The virtual memory maps use a C, B, and X column to indicate the caching policy for the region. Physical Address Range 0x0000 0000 - 0x7FFF FFFF... -
Page 79: Redboot Intel ® Iq80219 Physical Memory Map - Visual
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 5.4.3 Redboot Intel ® Figure 26. Redboot Intel IQ80310 Physical Memory Map 0000 0000h - 7FFF FFFFh 8000 0000h - 9001 FFFFh 9002 0000h - FFFF DFFFh Code / Data External Memory... -
Page 80: Redboot Intel ® Iq80219 Virtual Memory Map - Visual
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Software Reference 5.4.4 Redboot Intel ® Figure 27. Redboot Intel IQ80310 Virtual Memory Map 0x00000000 - 0x1fffffff 0x20000000 - 0x9fffffff 0xa0000000 - 0xb00fffff 0xc0000000 - 0xdfffffff 0xe0000000 - 0xe00fffff 0xF0000000 - 0xF0800000... -
Page 81: Redboot Intel ® Iq80219 Files
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 5.4.5 Redboot Intel Attached in the kit, find a copy of the Red Hat eCos for 80219r CD. Once the CD is installed, you may find: • The Redboot initialization code source files from the following location: From the installed directory: ..\Red Hat\eCos\packages\hal\arm\xscale\iq80321\current\include... -
Page 82: Redboot Intel ® Iq80219 Ddr Memory Initialization Sequence
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Software Reference 5.4.6 Redboot Intel In order to set the correct ECC bits, a DDR memory system (DIMM or discrete components) must be written to with a known value. This process requires 64-bit writes to the entire DDR memory intended for use. -
Page 83: Redboot Switching
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform 5.4.7 Redboot Switching • S8E1-2 ON: Enable GbE on the SPCI-X Bus. • S8E1-7 OFF: PCI-X Bridge hides devices using Private Space Address lines. • S4D1 ON-OFF-ON-OFF: GbE and Expansion Slot Private Space. - Page 84 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Software Reference This Page Left Intentionally Blank Board Manual...
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Page 85: Iq80310 And Iq80219 Comparisons
IQ80310 and IQ80219 Comparisons This appendix provides a brief description for differences between IQ80219 and IQ80310. Please also refer to application note: Migrating from the Intel General Purpose PCI Processor Application Note 273562. ® Table 90. Intel IQ80310 and Intel ®... - Page 86 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform IQ80310 and IQ80219 Comparisons This Page Left Intentionally Blank Board Manual...
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Page 87: Getting Started And Debugger
Debugger”. B.1.1 Purpose The purpose of this appendix is to help the user setup and become familiar with the Intel evaluation platform board (IQ80219) some of the development tools. This appendix steps the user through an example program using: •... -
Page 88: Related Web Sites
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger B.1.4 Related Web Sites • Macraigor: http://www.ocdemon.net/ • http://developer.intel.com/design/intelxscale/dev_tools/020523/index.htm • http://developer.intel.com/design/iio/80321.htm • http://developer.intel.com/design/iio/docs/iop321.htm • http://developer.intel.com/design/iio/swsup/Tester1LED.htm Board Manual... -
Page 89: Setup
• The IQ80219 plugs into a bus master PCI or PCI-X slot on the backplane or platform. Note: There are many dip switches on the evaluation board which are used to configure the IBM bridge. Use the dip switch and jumper sections of the Intel 3.10.2 to configure these switches. -
Page 90: Software Setup
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger B.2.2 Software Setup ATI Code|Lab is a plug-in to Microsoft Visual Studio 6.0; therefore, Microsoft Visual Studio 6.0 must be installed on the host system before installing ATI Code|Lab. To load ATI Code|Lab, run setup.exe under the program directory. -
Page 91: New Project Setup
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform New Project Setup B.3.1 Creating a New Project 1. Launch Code|Lab EDE and select “Tools/Customize/Add-ins/Macro Files”. a. Check “Code|Lab EDE” and click Close. 2. Select “File/New…/Project”, then “Code|Lab EDE Project Wizard” a. Fill-in the Project Name box with “Tester1LED”... -
Page 92: Configuration
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger B.3.2 Configuration On the tool bar, click on the icon that looks like a file folder with the letters “EDE” on it. When the mouse arrow is placed on it, a text box displays “Project Settings”. -
Page 93: Flashing With Jtag
This Flash programmer only supports certain file formats: Intel Hex, Motorola srec and standard elf (executable and linking format). RedBoot.s19 and RedBoot.srec are both srec files. Worcester.i32 is an ARM BootMonitor Intel Hex file. BootMonitor is an ARM version of a debug monitor, which is similar but not identical to RedBoot. -
Page 94: Using Flash Programmer
9. Click the Program button. 10. Click Browse and “Files of type:” All Files, then choose the “redboot_ROM.srec” file (downloaded http://developer.intel.com/design/intelxscale/dev_tools/020523/RedBoot Debug Monitor for the Intel® IQ80310/IQ80321/IQ80219 boards and uncompressed from developer.com). 11. Check box “Erase Target Flash Sector(s) Before Programming”. -
Page 95: Debugging Out Of Flash
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Debugging Out of Flash JTAG debuggers can be used on two levels; with or without the source code. When the Flash is programmed, the debugger can monitor the executable code, halt it, step through it, and monitor the memory and registers. -
Page 96: Running The Code|Lab Debugger
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger Running the Code|Lab Debugger This section is provided to get the system up and running in the Code|Lab Debug environment, but it is not intended as a full-functional tutorial. Please refer to the ATI Code|Lab Debug Reference Manual for more detailed information. -
Page 97: Manually Loading And Executing An Application Program
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform B.7.2 Manually Loading and Executing an Application Program 1. Launch the Code|Lab Debug Environment from the desktop icon. 2. Ensure “File…/Program Load Options/Load Executable and Symbols” is checked. 3. file, program load options, load executable and symbols. -
Page 98: Using Breakpoints
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger B.7.4 Using Breakpoints Note the small gray circles on the sidebar beside each line of source code. Single-click any of these gray circles and a red dot appears. The red dot represents a break point. Single-click the red dot to remove it, or click the “Remove all breakpoints”... -
Page 99: Stepping Through The Code
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform B.7.5 Stepping Through the Code The “led.c” file contains a function that is called from code in “blink.c”. Tis exercise steps through the code and utilizes a few of the most common step tools. -
Page 100: Exploring The Code|Lab Debug Windows
Memory window. The ATU header begins at 0xffffe100 and contains a known number (8086). Also look at the base and limit registers for the memory and Flash devices, at 0xffffe508 and ffffe688 respectively, since they were initialized by RedBoot. Use the Intel Processor Developer’s Manual, to see what the values mean. -
Page 101: Registers Window
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform B.8.6 Registers Window Close all the active windows, then bring up the Registers window. Resize the this window and its columns to get a good view of all the registers. Notice that there is a Flags tab at the bottom of this window. -
Page 102: Debugging Basics
B.9.2 Hardware and Software Breakpoints The following section provides a brief overview of breakpoints. See the Intel Purpose PCI Processor Developer’s Manual, for more detailed information. B.9.2.1 Software Breakpoints Software breakpoints are setup and utilized via debugger utilities (such as Code|Lab). -
Page 103: Exceptions/Trapping
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform B.9.3 Exceptions/Trapping A debug exception causes the processor to re-direct execution to a debug event handling routine. ® The Intel 80200 processor debug architecture defines the following debug exceptions: • instruction breakpoint •... - Page 104 Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger This Page Left Intentionally Blank Board Manual...
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Page 105: Getting Started And Debugger
C.1.1 Purpose The purpose of this appendix is to help the user setup and become familiar with the Intel ® IQ80321 Evaluation Platform Board (IQ80321) and, other related hardware and software. This appendix steps the user through an example program using: •... -
Page 106: Related Web Sites
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger C.1.4 Related Web Sites • Macraigor: http://www.ocdemon.net/ • http://developer.intel.com/design/intelxscale/dev_tools/020523/index.htm • http://developer.intel.com/design/iio/80321.htm • http://developer.intel.com/design/iio/docs/iop321.htm • http://developer.intel.com/design/iio/swsup/Tester1LED.htm Board Manual... -
Page 107: Setup
• The IQ80219 plugs into a bus master PCI or PCI-X slot on the backplane or platform. Note: There are many dip switches on the evaluation board which are used to configure the IBM bridge. Use the dip switch and jumper sections of the Intel 3.10.2 to configure these switches. -
Page 108: Software Setup
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger C.2.2 Software Setup ATI Code|Lab is a plug-in to Microsoft Visual Studio .NET, therefore Microsoft Visual Studio .NET must already be loaded on the system. To load ATI Code|Lab, run setup.exe under the program directory. -
Page 109: New Project Setup
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform New Project Setup C.3.1 Creating a New Project 1. Launch Code|Lab EDE for .NET. 2. On the Start Page, select “New Project”. a. The “New Projects” window appears. b. Select “Code|Lab Projects” under Project Types and name the project “Project80219” in the name field. -
Page 110: Configuration
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger C.3.2 Configuration Examine the main menu of Code|Lab EDE for .NET. • File • Edit Since Code|Lab is a plug-in to Visual Studio, some of these menu items are Visual Studio and some are specific to Code|Lab. -
Page 111: Flashing With Jtag
This Flash programmer only supports certain file formats: Intel Hex, Motorola srec and standard elf (executable and linking format). RedBoot.s19 and RedBoot.srec are both srec files. Worcester.i32 is an ARM BootMonitor Intel Hex file. BootMonitor is an ARM version of a debug monitor, which is similar but not identical to RedBoot. -
Page 112: Using Flash Programmer
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger C.4.2 Using Flash Programmer Note: The parallel port must be set to EPP mode or the Macraigor Raven will not work properly. Download the RedBoot executable files from the following location: http://developer.intel.com/design/intelxscale/dev_tools/020523/RedBoot Debug Monitor for the... -
Page 113: Debugging Out Of Flash
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Debugging Out of Flash JTAG debuggers can be used on two levels; with or without the source code. When the Flash is programmed, the debugger can monitor the executable code, halt it, step through it, and monitor the memory and registers. -
Page 114: Running The Code|Lab Debugger
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger Running the Code|Lab Debugger This section is provided to get the system up and running in the Code|Lab Debug environment, but it is not intended as a full-functional tutorial. Please refer to the ATI Code|Lab Debug Reference Manual for more detailed information. -
Page 115: Displaying Source Code
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform C.7.3 Displaying Source Code 1. Launch the Code|Lab EDE Debugger and open the “Tester1LED” ELF program. Note: Use the File/Recent Programs menu for quick access. 2. Select the “Files” view in the lower tab of the WorkSpace window. -
Page 116: Stepping Through The Code
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger C.7.5 Stepping Through the Code The “led.c” file contains a function that is called from code in “blink.c”. This exercise steps through the code and utilizes a few of the most common step tools. -
Page 117: Exploring The Code|Lab Debug Windows
Memory window. The ATU header begins at 0xffffe100 and contains a known number (8086). Also look at the base and limit registers for the memory and Flash devices, at 0xffffe508 and ffffe688 respectively, since they were initialized by RedBoot. Use the Intel Processor Developer’s Manual, to see what the values mean. -
Page 118: Registers Window
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger C.8.6 Registers Window Close all the active windows, then bring up the Registers window. Resize the this window and its columns to get a good view of all the registers. Notice that there is a Flags tab at the bottom of this window. -
Page 119: Debugging Basics
C.9.2 Hardware and Software Breakpoints The following section provides a brief overview of breakpoints. See the Intel Purpose PCI Processor Developer’s Manual, for more detailed information. C.9.2.1 Software Breakpoints Software breakpoints are setup and utilized via debugger utilities (such as Code|Lab). -
Page 120: C.9.3 Exceptions/Trapping
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform Getting Started and Debugger C.9.3 C.9.3 Exceptions/Trapping A debug exception causes the processor to re-direct execution to a debug event handling routine. The ® Intel 80200 processor debug architecture defines the following debug exceptions: •...