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PREPARATION FOR USE
Table 2-5.
Jumper Listing By Numerical Order (continued)
Jumper
Number
E246 through
E253
E254 through
E262
E263 through
E276
E277-E278*
E279
Description
Provides access to the inputs to the 3-state octal
transceiver buffering the Multibus interrupt lines
(INTO/ through INT7/).
Non-user configurable jumpers that select the address
decode mode for the 3625A Decode PROM.
Non-user configurble jumpers that select the 8203 RAM
Controller mode of operation.
Connects the +5v bus to the +5v battery backup bus when
installed.
Provides more conditions on generation of the TIME OUT
INTR/ signal for use with iRMX 86 software.
The ORing
of E279-E133 via the "OR" function provided in the
interrupt jumper matrix disables a failsafe timeout
restart when executing a HALT instruction under iRMX 86
software.
2-12.
RAM Address Configuration Jumpers
The RAM on the iSBC 86/14/30 board is assigned two addresses; hereafter
referred to as the local address and the Multibus address.
The local
address is a 16-bit address that must be used by the local processor to
access the local RAM; the Multibus address is a 24-bit address that must
be used by a system bus master (other than the on-board CPU) to access
the dual port portion of the local RAM.
the iSBC 86/14 and iSBC 86/30 boards provide several jumper options for
assigning a Multibus address to the dual port RAM and for selecting the
amount of dual port RAM on the board.
The jumper posts are the same for
the iSBC 86/14 and the iSBC 86/30 boards, however, the configuration of
the jumpers on the two boards is different because of the memory chip
capacity differences.
So, the following text separates the jumper
configuring descriptions for each board.
Configuration of the Multibus
address select jumpers is described in the following text.
2-23
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