Isbx Bus Interface Jumper Configuration - Intel iSBC 86/14 Hardware Reference Manual

PREPARATION FOR USE
bit 2 is a user configurab1e output providing the NMI MASK/ signal, bit 3
is a user configurab1e output providing the OVERRIDE/ signal, bit 4 is a
user configurab1e output providing the BUS INTR OUT 1 signal as an
interrupt request to the Mu1tibus interface, bit 5 is dedicated to
generation of BUS INTR OUT 2 and to driving the LED labeled DS2, bit 6 is
dedicated to controlling the LED labeled DS3 on the board, and bit 7 is
dedicated to enabling the latch. The uses of the jumper selectable bits
of the Status Register are described in the following paragraphs •
•
As
shipped, the iSBC 86/14/30 boards contain jumpers E28-E32 and E30-E31
tieing the GATE inputs to the PIT at a HIGH level. If control
0
the GATE
inputs to the PIT is required, connect the GATE signals (at E28 and E31)
to the output signals from the status register (jumper posts E29 and E35)
and program the status register via I/O port addresses C8 through DF (all
odd addresses) to output the proper signal level.
The NMI mask enable jumper E26-E27 is installed into the iSBC 86/14/30
board, when configured as shipped. Since the contents of the status
register bit 3 is zero initially, the jumper masks the NMI interrupt,
thereby disabling the NMI interrupt from reaching the 8086-2 CPU. By
programming a 1 into status register bit 3, you can enable the 8086-2 to
receive an NMI interrupt.
The OVERRIDE/ signal jumper E22-E23 is installed into the iSBC 86/14/30
board, when configured as shipped. The OVERRIDE/ signal from the status
register operates in the same manner as the NMI/ signal does; the
contents of status register bit 4 is zero initially. This fact plus the
jumper E22-E23 activates the OVERRIDE/ signal, thereby disabling the
LOCK/ signal from locking the dual port RAM on the Multibus interface.
By programming a 1 into status register bit 4, you can assert the LOCK/
signal.
The BUS INTR OUT 1 signal enable jumper E24-E25 is not installed into the
iSBC 86/14/30 board, when configured as shipped. Since the contents of
the status register bit 5 is zero initially, the jumper must be installed
and bit 5 must be programmed to output a HIGH if the BUS INTR OUT 1
signal is to generate a Multibus interrupt output (INTO/ through INT7/).
Additional jumper configuration is required at the interrupt jumper
matrix to place the signal onto the Multibus interface.
2-26. iSBX Bus Interface Jumper Configuration
The iSBX bus interfaces on the iSBC 86/14/30 board contain only four
signals that may be configured via user installed jumpers. Those signals
are the Mu1timodu1e option signals (OPTO/ and OPTI/) and the Multimodu1e
interrupt signals (MINTRO/ and MINTRI/) from each iSBX Bus connector.
Configuration of the jumpers should take into account the requirements of
the Mu1timodule boards as specified in the respective Multimodu1e board
hardware reference manual.
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