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PREPARATION FOR USE
Table 2-5.
Jumper Listing By Numerical Order (continued)
Jumper
Number
Description
E31-E35
E33-E34
E36-E37
E38-E39
E4D-E41*
E42-E43*
E44-E53*,
E45-E54* ,
E46-E55*,
E4 7-E56*,
E48-E57*,
E49-E58* ,
E50-E59*,
E51-E60*
E52-E61*
E62
E63
E65, E66
E67
E68
E69
E7D-E71
E72-E74
E73-E75
E76-E77
E78, E80,
E79
E81
Provides programmable control of the GATE input to
8253-5 PIT timer 1.
Selects operation of the interrupt circuitry in a bus
vectored system when installed; remove for exclusively
non-bus vector operation.
Selects either 5 MHz clock (installed) or 8 MHz clock
(removed) operation for the 8086-2 CPU.
Enables generation of the failsafe timeout interrupt
request to the 8259A PIC when installed.
Not user configurable.
Disables status latch and edge interrupt flipflop when
installed.
Connects the 8255A PPI Port C I/O signals to the J1
connector.
Connects the direction control for the 8255A PPI port A
I/O signal buffer to ground, selecting output mode when
installed.
TEST signal to 8086-2 CPU
PA INTR signal input from the parallel port to the
interrupt jumper matrix.
I/O signals to the parity generation Multimodule board.
EXT CLK input from the parallel port to the 825lA PCI
or 8253-5 PIT device.
STXD signal from the parallel I/O port to either the
serial I/O port or the clock genertor circuitry.
PFSN/ single input from the P2 connector to the
parallel I/O port.
Enables +5 volts onto the auxiliary connector at pin 23
when installed.
Enables -12 volts onto the auxiliary connector at pin
19 when installed.
Enables +12 volts onto the auxiliary connector at pin
22 when installed.
Enables generation of CTS signal from RTS signal on the
serial I/O interface.
Configurable I/O line access on the serial I/O
interface.
Output of a signal amplifier; for use when configuring
an output onto the serial I/O interface.
2-19
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