Connector Pi Signal Descriptions - Intel iSBC 86/14 Hardware Reference Manual

Intel single board computer hardware reference manual
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PREPARATION FOR USE
Table 2-20.
Connector PI Signal Descriptions
Signal
Functional Description
ADRO/-ADRF/
ADR10/-ADR13/
BCLK/
BHEN/
BPRN/
BPRO/
BREQ/
BUSY/
CBRQ/
CCLK/
DATO/-DATF/
INR1/
Address-.
These 20 lines transmit the address of the
memory location or I/O port to be accessed.
ADR13/ is the
most significant address bit.
Bus Clock.
Used to synchronize the bus contention logic on
all bus masters.
When generated by the iSBC 86/14/30
board, BCLK/ has a period of 102.5 nanoseconds (9.83 MHz)
with a 50 percent duty cycle.
Byte High Enable.
Used to select the upper byte (bits 8
through F) of a la-bit word.
The signal is functional only
in systems that incorporate 16-bit memory and I/O devices.
Bus Priority In.
Indicates to a particular bus master that
no higher priority master is requesting use of the bus.
BPRN/ is synchronized with BCLK/.
Bus Priority Out.
In serial (daidy chain) priority
resolution schemes, BPRO/ must be connected to the BPRN/
input of the bus master with the next lower bus priority.
Bus Request.
In parallel priority resolution schemes,
BREQ/ indicates that a particular bus master requires
control of the bus for one or more data transfers.
BREQ/
is synchronized with BCLK/.
Bus Busy.
Indicates that the bus is in use and prevents
all other bus masters from gaining control of the bus.
BUSY/ is synchronized with BCLK/.
Common Bus Request.
Indicates that a bus master wishes
control of the bus but does not presently have control.
As
soon as control
0
the bus is obtained, the requesting bus
controller releases the CBRQ/ signal.
Constant Clock.
Provides a clock signal of constant
frequency for use by other system modules.
When generated
by the iSBC 86/14/30 board, CCLK/ has a period of 102.5
nanoseconds (9.83
MHz)
with a 50 percent duty cycle.
Data.
These 16 bidirectional data lines transmit and
receive data to and from the addressed memory location or
I/O port.
DATF/ is the most-significant bit.
Inhibit RAM.
For system application, allows iSBC 86/14/30
board dual port RAM addresses to be overlaid by another RAM
in the system.
2-53

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