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post max max Output Comparison (Continued)
TABLE 11-6
Output Displayed
0>PLL Reset.....
0>Initialize I2C Controller
0>Init CPU
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0>
Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 8:1 12:1, sys 200 MHz, CPU 1600 MHz, mem
133 MHz.
0> UltraSPARC[TM] IIIi, Version 3.4
0>Init Memory.....
0>Probe Dimms
0>Init Mem Controller Sequence
0>Clear TLU loopback for PCI-E
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO: 2048MB Bank 0, Dimm Type X4
0>INFO: No memory detected in Bank 1
0>INFO: No memory detected in Bank 2
0>INFO: No memory detected in Bank 3
0>
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO: 2048MB Bank 0, Dimm Type X4
0>INFO: No memory detected in Bank 1
0>INFO: No memory detected in Bank 2
0>INFO: No memory detected in Bank 3
0>
0>Data Bitwalk on Master
0> Test Bank 0.
0>Address Bitwalk on Master
0>Addr walk mem test on CPU 0 Bank 0:
00000000.00000000 to 00000000.80000000.
0>Set Mailbox
0>Final mc1 is 1000000a.1e581c61
11-8
Sun Ultra 45 and Ultra 25 Workstations Service and Diagnostics Manual • May 2006
What Is Happening
Initializations and setups are
repeated.
New timing ratios and frequencies
are displayed.
Repeated initialization continues.
Memory is probed.
CPU data pins are tested.
Where found, memory is tested.
CPU address pins are tested.
Mailbox region is set in memory.
Memory control register1 is set.
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