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post max max Output Comparison (Continued)
TABLE 11-6
Output Displayed
reset reason: 0000.0000.0000.0001
Fire TLU-A OE Error status: 0003.0100.0000.0100
@(#)OBP 4.21.x 2005/09/28 16:12 Sun Ultra 45
Clearing TLBs
Executing Power On Self Test
Q0>
0>@(#) Sun Ultra 45 POST 4.21.x 2005/11/05 19:58
/dat/fw/common-source/firmware_re/post/post-build-
4.21.0/Ultra/Ultra45/integrated
0>Copyright © 2005 Sun Microsystems, Inc. All rights
reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
0>Soft Power-on RST thru SW
0>OBP->POST Call with %o0=00001000.01014000.
0>Diag level set to MAX.
0>Verbosity level set to MAX.
0>MFG scrpt mode set NORM
0>I/O port set to TTYA.
0>Start Selftest.....
0>CPUs present in system: 0
0>Test CPU(s).....
0>Initialize I2C Controller
0>Init CPU
0>DMMU
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0>
Size = 00000000.00100000...
0>L2 Cache Tags Test
0>Scrub and Setup L2 Cache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Test
Mailbox
0>Scrub Mailbox
11-6
Sun Ultra 45 and Ultra 25 Workstations Service and Diagnostics Manual • May 2006
(firmware_re)
What Is Happening
OpenBoot PROM prepares to run
POST
.
POST build version and date is
displayed.
POST build path is displayed.
Copyright and license are
displayed.
CPU0 is acknowledged and POST
configuration is read from
register.
2
CPU, I
C controller, data memory
management unit (DMMU), and
instruction memory management
unit (IMMU) are initialized.
L2 cache is set up and scrubbed
(data values set to defaults).
DMMU is set up.
Mailbox region is checked and
initialized in L2 cache.
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