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post max max Output Comparison (Continued)
TABLE 11-6
Output Displayed
0>CPU Tick and Tick Compare Registers Test
0>CPU Stick and Stick Compare Registers Test
0>Set Timing
0> UltraSPARC[TM] IIIi, Version 3.4
0>Interrupt Crosscall.....
0>Setup Int Handlers
0>MB:
Part-Dash-Rev#:
000225
0>CPU0 DIMM 0:
0>Part#: 18VDDF12872Y-335D3 Serial#: 71fe1ec9 Date
Code:
0506
Rev#:
0>CPU0 DIMM 1:
0>Part#: 18VDDF12872Y-335D3 Serial#: 71fe1e32 Date
Code:
0506
Rev#:
0>Set CPU/System Speed
0>MCR Timing index = 00000000.00000007
0>..
0>Init Memory.....
0>Probe Dimms
0>Init Mem Controller Regs
0>Set JBUS config reg
0>IO-Bridge unit 1 init test
0>Clear TLU loopback for PCI-E
0>Do PLL reset
0>Setting timing to 8:1 12:1, system frequency 200
MHz, CPU frequency 1600 MHz
ø0>Soft Power-on RST thru SW
3753279-02-0C
0300
0300
What Is Happening
Operation of TICK registers is
verified.
Operation of STICK registers is
verified.
Motherboard timing is to be
configured.
CPU version is identified.
Interrupt handlers are set up.
Motherboard part number and
Serial#:
serial number is read from FRU
ID.
DIMM part numbers, serial
numbers, date codes, and
revisions are read from the
DIMM's internal firmware.
Jumpers for CPU and JBus
frequency are read.
Memory is initialized.
Presence of DIMMs is checked.
Memory controller registers are
initialized.
JBus configuration register is set.
I/O bridge chip is initialized.
Phase-locked loop (PLL) is reset
for the selected frequencies.
Soft reset.
Chapter 11 Power-On Self-Test
11-7
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