Mitsubishi Electric MELSEC Q Series User Manual page 48

Programmable controller multiple cpu system
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*1: "No. of CPUs" indicates the number of CPU modules set at "No. of PLC" in the Multiple CPU settings screen of PLC parameter.
*2: When the PC CPU module is mounted, the maximum number of mountable I/O modules is the result of "65 - (Number of CPUs + 1)
(when using the Q00UCPU, Q01UCPU: 24 - (Number of CPUs + 1)) (when using the Q02UCPU: 37 - (Number of CPUs + 1))".
*3: When the Motion CPU or PC CPU module is mounted on the multiple CPU system, Q3 RB, Q6 RB, and Q6 RP are not available.
*4: When the Q00UCPU, Q01UCPU, Q02UCPU is used as the CPU module 1, up to three CPU modules can be mounted.
Therefore, the CPU No. 4 does not exist.
*5: These versions can be used for the Q02UCPU, Q03UDCPU, Q04UDHCPU, and Q06UDHCPU. For software versions available for a
Universal model QCPU other than the above, refer to Section 2.3.
*6: Available for Built-in Ethernet port QCPUs only.
*7: When a Universal model QCPU (except Q00UCPU, Q01UCPU, Q02UCPU) or Motion CPU (Q172DCPU or Q173DCPU) is used as any
of CPUs No.2 to No.4, clock data in CPU No.1 can be used.
*8: When CPU No.1 is the Q00UCPU, Q01UCPU, Q02UCPU, the communication by the auto refresh using the multiple CPU high speed
transmission area is not available.
*9: When CPU No.1 is the Q02UCPU, the multiple CPU high speed transmission area cannot be set up.
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